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SN74LS112AJS PDF预览

SN74LS112AJS

更新时间: 2024-11-04 13:00:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
4页 150K
描述
LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16

SN74LS112AJS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.18
Is Samacsys:N系列:LS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm逻辑集成电路类型:J-K FLIP-FLOP
位数:2功能数量:2
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):20 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:45 MHzBase Number Matches:1

SN74LS112AJS 数据手册

 浏览型号SN74LS112AJS的Datasheet PDF文件第2页浏览型号SN74LS112AJS的Datasheet PDF文件第3页浏览型号SN74LS112AJS的Datasheet PDF文件第4页 
SN54/74LS112A  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and  
asynchronous set and clear inputs to each flip-flop. When the clock goes  
HIGH, the inputs are enabled and data will be accepted. The logic level of the  
J and K inputs may be allowed to change when the clock pulse is HIGH and  
thebistablewillperformaccordingtothetruthtableaslongasminimumset-up  
and hold time are observed. Input data is transferred to the outputs on the  
negative-going edge of the clock pulse.  
DUAL JK NEGATIVE  
EDGE-TRIGGERED FLIP-FLOP  
LOW POWER SCHOTTKY  
LOGIC DIAGRAM (Each Flip-Flop)  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
MODE SELECT — TRUTH TABLE  
INPUTS  
OUTPUTS  
OPERATING MODE  
S
D
C
J
K
Q
Q
D
Set  
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
X
X
X
h
h
l
H
L
H
q
L
H
q
L
H
H
q
H
L
LOGIC SYMBOL  
Reset (Clear)  
*Undetermined  
Toggle  
Load “0” (Reset)  
Load “1” (Set)  
Hold  
h
l
l
q
* BothoutputswillbeHIGHwhilebothS andC areLOW,buttheoutputstates  
D
D
are unpredictable if S and C go HIGH simultaneously.  
D
D
H, h = HIGH Voltage Level  
L, I = LOW Voltage Level  
X = Don’t Care  
l, h (q) = Lower case letters indicate the state of the referenced input (or output)  
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.  
FAST AND LS TTL DATA  
5-185  

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