Datasheet > SN74LS109

SN74LS109

更新时间： 2024-11-10 23:03:15

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
4页	99K
描述
LOW POWER SCHOTTKY

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中文翻译

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数据手册

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SN74LS109 数据手册

The SN74LS109A consists of two high speed completely

independent transition clocked JK flip-flops. The clocking operation

is independent of rise and fall times of the clock waveform. The JK

design allows operation as a D flip-flop by simply connecting the J and

K pins together.

http://onsemi.com

LOW

POWER

SCHOTTKY

MODE SELECT – TRUTH TABLE

INPUTS

OUTPUTS

OPERATING MODE

Set

Reset (Clear)

*Undetermined

Load “1” (Set)

Hold

Toggle

Load “0” (Reset)

PLASTIC

N SUFFIX

CASE 648

Both outputs will be HIGH while both S and C are LOW, but the output

D D

states are unpredictable if S and C go HIGH simultaneously.

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one set-up time prior to the LOW to HIGH clock transition.

SOIC

D SUFFIX

CASE 751B

GUARANTEED OPERATING RANGES

Symbol

Parameter

Supply Voltage

Min

4.75

Typ

5.0

Max

5.25

Unit

Operating Ambient

Temperature Range

°C

ORDERING INFORMATION

Output Current – High

Output Current – Low

–0.4

8.0

Device

Package

16 Pin DIP

16 Pin

Shipping

SN74LS109AN

SN74LS109AD

2000 Units/Box

2500/Tape & Reel

Semiconductor Components Industries, LLC, 1999

Publication Order Number:

December, 1999 – Rev. 6

SN74LS109A/D

12 3 4

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与SN74LS109相关器件

型号	品牌	获取价格	描述	数据表
SN74LS109A	ONSEMI	获取价格	LOW POWER SCHOTTKY
SN74LS109A	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
SN74LS109AD	TI	获取价格	DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
SN74LS109AD	ONSEMI	获取价格	LOW POWER SCHOTTKY
SN74LS109AD	MOTOROLA	获取价格	LS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, SO
SN74LS109AD3	TI	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,SOP,16PIN,PLASTIC
SN74LS109ADE4	TI	获取价格	LS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, GR
SN74LS109ADR	TI	获取价格	具有清零和预置端的双路负边沿触发式 J-K 触发器 \| D \| 16 \| 0 to 70
SN74LS109ADR2	ONSEMI	获取价格	LS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PL
SN74LS109ADR2	ROCHESTER	获取价格	J-Kbar Flip-Flop, LS Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output,