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SN74HSTL162822DGG

更新时间： 2024-10-01 22:33:39
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德州仪器 - TI 存储双倍数据速率
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14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

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SN74HSTL162822DGG 数据手册

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SN74HSTL162822  
14-BIT TO 28-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH  
SCES091A – DECEMBER 1996 – REVISED APRIL 1997  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
Inputs Meet JEDEC HSTL Standard  
JESD8-6  
1Q2  
2Q1  
1Q1  
GND  
D1  
2Q2  
1Q3  
GND  
2Q3  
1Q4  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
All Outputs Have Equivalent 25-Ω Series  
Resistors  
3
4
Packaged in Plastic Thin Shrink  
Small-Outline Package  
5
D2  
D3  
V
6
CC  
2Q4  
1Q5  
GND  
2Q5  
1Q6  
7
description  
V
8
CC  
D4  
D5  
D6  
GND  
D7  
9
This 14-bit to 28-bit D-type latch is designed for  
3.15-V to 3.45-V V operation. HSTL levels are  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
CC  
expected on the inputs. LVTTL levels are driven  
on the Q outputs.  
V
CC  
2Q6  
1Q7  
GND  
2Q7  
2Q8  
GND  
1Q8  
2Q9  
All outputs are designed to sink up to 12 mA and  
include 25-Ω series resistors to reduce overshoot  
and undershoot.  
1LE  
V
CC  
V
REF  
GND  
The SN74HSTL162822 is particularly suitable for  
driving an address bus to two banks of memory.  
Each bank of 14 outputs is controlled with its own  
latch-enable (LE) input.  
GND  
2LE  
D8  
GND  
D9  
V
CC  
Each of the 14 data (D) inputs is tied to the inputs  
of two D-type latches, which provide true data at  
the outputs. While LE is low, the outputs (Q) of the  
corresponding 14 latches follow the D inputs.  
When LE is taken high, the Q outputs are latched  
at the levels set up at the D inputs.  
1Q9  
D10  
D11  
2Q10  
GND  
1Q10  
2Q11  
V
CC  
D12  
D13  
D14  
GND  
1Q14  
2Q14  
1Q13  
V
CC  
The SN74HSTL162822 is characterized for  
operation from –40°C to 90°C.  
1Q11  
2Q12  
GND  
1Q12  
2Q13  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Q
LE  
D
H
L
L
L
H
L
†
Q
0
H
X
†
Output level before the  
indicated steady-state input  
conditions were established  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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