Datasheet > SN74HCT595PWR

SN74HCT595PWR

更新时间： 2024-11-24 02:51:35

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德州仪器 - TI		/
页数	文件大小	规格书
26页	1474K
描述
SN74HCT595 8-Bit Shift Registers with 3-State Output Registers

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SN74HCT595PWR 数据手册

SN74HCT595

SCLS880A – OCTOBER 2021 – REVISED DECEMBER 2021

SN74HCT595 8-Bit Shift Registers with 3-State Output Registers

1 Features

3 Description

•

LSTTL input logic compatible

– V_IL(max)= 0.8 V, V_IH(min)= 2 V

CMOS input logic compatible

– I_I≤ 1 µA at V_OL, V_OH

The SN74HCT595 device contains an 8-bit, serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. The storage register has parallel

3-state outputs. Separate clocks are provided for

both the shift and storage register. The shift register

has a direct overriding clear (SRCLR) input, serial

(SER) input, and a serial output (Q_H') for cascading.

When the output-enable (OE) input is high, the

storage register outputs are in a high-impedance

state. Internal register data and serial output (Q_H') are

not impacted by the operation of the OE input.

•

4.5 V to 5.5 V operation

Supports fanout up to 10 LSTTL loads

Shift register has direct clear

Extended ambient temperature range: –40°C to

+125°C, T_A

2 Applications

Device Information⁽¹⁾

•

Output expansion

LED matrix control

7-segment display control

8-bit data storage

PART NUMBER

PACKAGE

BODY SIZE (NOM)

SN74HCT595PW

TSSOP (16) 5.00 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

RCLK

SRCLR

SRCLK

SER

Q_A

Q_B

Q_C

Q_D

Q_E

Q_F

Q_G

Q_H

Q_H’

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

12 3 4 5 6 7...26

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