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SN74HC623NE4 PDF预览

SN74HC623NE4

更新时间： 2024-09-23 21:14:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 502K
描述
HC/UH SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDIP20, ROHS COMPLIANT, PLASTIC, MS-001AD, DIP-20

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中文翻译

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SN74HC623NE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.45控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：HC/UH
JESD-30 代码：R-PDIP-T20JESD-609代码：e4
长度：25.4 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 VProp。Delay @ Nom-Sup：26 ns
传播延迟（tpd）：170 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：7.62 mmBase Number Matches：1

SN74HC623NE4 数据手册

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SCLS149C – DECEMBER 1982 – REVISED DECEMBER 2002  
SN54HC623 . . . J OR W PACKAGE  
SN74HC623 . . . DW, N, OR NS PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
D
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
OEAB  
A1  
V
CC  
OEBA  
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Typical t = 8 ns  
pd  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
B1  
B2  
B3  
B4  
±6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Lock Bus-Latch Capability  
True Logic  
B5  
13 B6  
12 B7  
description/ordering information  
11  
B8  
These octal bus transceivers are designed for  
asynchronous two-way communication between  
data buses. The control-function implementation  
allows for maximum flexibility in timing.  
SN54HC623 . . . FK PACKAGE  
(TOP VIEW)  
The ’HC623 devices allow data transmission from  
the A bus to the B bus or from the B bus to the A  
bus, depending upon the logic levels at the  
output-enable (OEAB and OEBA) inputs.  
3
2
1
20 19  
18  
B1  
B2  
B3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
OEAB and OEBA disable the device so that the  
buses are effectively isolated. The dual-enable  
configuration gives the transceivers the capability  
to store data by simultaneously enabling OEAB  
and OEBA. Each output reinforces its input in this  
transceiver configuration. When both OEAB and  
OEBA are enabled and all other data sources to  
the two sets of bus lines are in the high-impedance  
state, both sets of bus lines (16 total) remain at  
their last states. The 8-bit codes appearing on the  
two sets of buses are identical.  
15 B4  
14  
B5  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HC623N  
SN74HC623N  
Tube  
SN74HC623DW  
SN74HC623DWR  
SN74HC623NSR  
SNJ54HC623J  
SNJ54HC623W  
SNJ54HC623FK  
–40°C to 85°C  
SOIC – DW  
HC623  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
CDIP – J  
HC623  
SNJ54HC623J  
SNJ54HC623W  
SNJ54HC623FK  
–55°C to 125°C  
CFP – W  
LCCC – FK  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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