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SN74HC365PWTG4 PDF预览

SN74HC365PWTG4

更新时间： 2024-09-27 15:52:15
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
19页 1074K
描述
Bus Driver, HC/UH Series, 1-Func, 6-Bit, True Output, CMOS, PDSO16, GREEN, PLASTIC, TSSOP-16

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中文翻译

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SN74HC365PWTG4 技术参数

生命周期：Contact Manufacturer包装说明：TSSOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56Is Samacsys：N
其他特性：WITH DUAL OUTPUT ENABLE系列：HC/UH
JESD-30 代码：R-PDSO-G16长度：5 mm
逻辑集成电路类型：BUS DRIVER位数：6
功能数量：1端口数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：150 ns
座面最大高度：1.2 mm最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

SN74HC365PWTG4 数据手册

 浏览型号SN74HC365PWTG4的Datasheet PDF文件第2页浏览型号SN74HC365PWTG4的Datasheet PDF文件第3页浏览型号SN74HC365PWTG4的Datasheet PDF文件第4页浏览型号SN74HC365PWTG4的Datasheet PDF文件第5页浏览型号SN74HC365PWTG4的Datasheet PDF文件第6页浏览型号SN74HC365PWTG4的Datasheet PDF文件第7页 
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SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003  
SN54HC365 . . . J OR W PACKAGE  
SN74HC365 . . . D, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Drive Bus  
Lines, Buffer-Memory Address Registers,  
or Drive Up To 15 LSTTL Loads  
OE1  
A1  
V
CC  
OE2  
A6  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
D
D
D
D
D
True Outputs  
Y1  
Low Power Consumption, 80-µA Max I  
CC  
A2  
Y6  
Typical t = 10 ns  
pd  
6-mA Output Drive at 5 V  
Y2  
12 A5  
11  
10  
9
A3  
Y5  
A4  
Y4  
Low Input Current of 1 µA Max  
Y3  
GND  
description/ordering information  
SN54HC365 . . . FK PACKAGE  
(TOP VIEW)  
These hex buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters. The ’HC365 devices contain six  
independent buffers/drivers with dual-gated  
output-enable (OE1 and OE2) inputs. When OE1  
and OE2 are both low, the devices pass  
noninverted data from the A inputs to the  
Y outputs. If either (or both) output-enable  
terminal(s) is high, the outputs are in the  
high-impedance state.  
3
2
1
20 19  
18  
A6  
Y6  
NC  
Y1  
A2  
NC  
Y2  
A3  
4
5
6
7
8
17  
16  
15 A5  
14  
9 10 11 12 13  
Y5  
NC − No internal connection  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 90  
SN74HC365N  
SN74HC365N  
SN74HC365D  
SN74HC365DR  
SN74HC365DT  
SN74HC365NSR  
SN74HC365PW  
SN74HC365PWR  
SN74HC365PWT  
SNJ54HC365J  
SNJ54HC365W  
SNJ54HC365FK  
SOIC − D  
SOP − NS  
HC365  
HC365  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
TSSOP − PW  
HC365  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC365J  
SNJ54HC365W  
SNJ54HC365FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

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