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SN74HC126PWTE4 PDF预览

SN74HC126PWTE4

更新时间： 2024-11-20 05:17:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
19页 528K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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中文翻译

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SN74HC126PWTE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.02控制类型：ENABLE HIGH
系列：HC/UHJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.006 A湿度敏感等级：1
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：2/6 V
Prop。Delay @ Nom-Sup：30 ns传播延迟（tpd）：188 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74HC126PWTE4 数据手册

 浏览型号SN74HC126PWTE4的Datasheet PDF文件第2页浏览型号SN74HC126PWTE4的Datasheet PDF文件第3页浏览型号SN74HC126PWTE4的Datasheet PDF文件第4页浏览型号SN74HC126PWTE4的Datasheet PDF文件第5页浏览型号SN74HC126PWTE4的Datasheet PDF文件第6页浏览型号SN74HC126PWTE4的Datasheet PDF文件第7页 
SN54HC126, SN74HC126  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS103E – MARCH 1984 – REVISED JULY 2003  
Wide Operating Voltage Range of 2 V to 6 V  
Typical t = 11 ns  
pd  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive Up  
To 15 LSTTL Loads  
6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Low Power Consumption, 80-µA Max I  
CC  
SN54HC126 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC126 . . . J OR W PACKAGE  
SN74HC126 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
12  
11  
10  
9
1Y  
4A  
17  
16  
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
15 NC  
14  
9 10 11 12 13  
2Y  
3OE  
2A  
8
GND  
3Y  
NC – No internal connection  
description/ordering information  
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled  
when the associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pullup  
resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
SOIC – D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC126N  
SN74HC126N  
SN74HC126D  
SN74HC126DR  
SN74HC126DT  
SN74HC126NSR  
SN74HC126DBR  
SN74HC126PW  
SN74HC126PWR  
SN74HC126PWT  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
HC126  
–40°C to 85°C  
SOP – NS  
HC126  
HC126  
SSOP – DB  
TSSOP – PW  
HC126  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HC126J  
SNJ54HC126W  
SNJ54HC126FK  
–55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

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