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SN74HC125N3 PDF预览

SN74HC125N3

更新时间: 2024-11-20 11:56:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 637K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN74HC125N3 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.02Is Samacsys:N
控制类型:ENABLE LOW系列:HC/UH
JESD-30 代码:R-PDIP-T14长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.0078 A位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/6 V
Prop。Delay @ Nom-Sup:150 ns传播延迟(tpd):190 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

SN74HC125N3 数据手册

 浏览型号SN74HC125N3的Datasheet PDF文件第2页浏览型号SN74HC125N3的Datasheet PDF文件第3页浏览型号SN74HC125N3的Datasheet PDF文件第4页浏览型号SN74HC125N3的Datasheet PDF文件第5页浏览型号SN74HC125N3的Datasheet PDF文件第6页浏览型号SN74HC125N3的Datasheet PDF文件第7页 
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ꢖ ꢗꢕ ꢄ ꢘ ꢙꢀꢕꢌꢕ ꢑ ꢚ ꢋꢕ ꢏ ꢋꢕ  
SCLS104D − MARCH 1984 − REVISED AUGUST 2003  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
D
D
D
Typical t = 11 ns  
pd  
6-mA Output Drive at 5 V  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive Up  
To 15 LSTTL Loads  
Low Input Current of 1 µA Max  
D
Low Power Consumption, 80-µA Max I  
CC  
SN54HC125 . . . FK PACKAGE  
(TOP VIEW)  
SN54HC125 . . . J OR W PACKAGE  
SN74HC125 . . . D, DB, N, NS, OR PW PACKAGE  
(TOP VIEW)  
1OE  
1A  
V
CC  
13 4OE  
1
2
3
4
5
6
7
14  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
12  
11  
10  
9
1Y  
4A  
17  
16  
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
15 NC  
14  
9 10 11 12 13  
2Y  
3OE  
2A  
8
GND  
3Y  
NC − No internal connection  
description/ordering information  
These quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled  
when the associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC125N  
SN74HC125N  
SN74HC125D  
SN74HC125DR  
SN74HC125DT  
SN74HC125NSR  
SN74HC125DBR  
SN74HC125PWR  
SN74HC125PWT  
SNJ54HC125J  
SNJ54HC125W  
SNJ54HC125FK  
HC125  
−40°C to 85°C  
SOP − NS  
HC125  
HC125  
SSOP − DB  
TSSOP − PW  
HC125  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC125J  
SNJ54HC125W  
SNJ54HC125FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢚ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢱꢗ ꢐꢙ ꢏꢎ ꢓ ꢙꢘꢲꢂ ꢘꢂꢈ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢚ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢈ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ  
ꢞꢦ  
ꢜꢤ  
ꢠꢦ  
ꢦꢟ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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