Datasheet > 逻辑 > 栅极> SN74HC10QPWREP

SN74HC10QPWREP

更新时间： 2024-11-01 12:21:51

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
11页	540K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATE

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SN74HC10QPWREP 数据手册

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ

ꢋ ꢌꢍꢊ ꢎꢉ ꢏ ꢈꢍꢁ ꢊꢐꢋ ꢊꢑ ꢀꢍ ꢋ ꢍꢒꢉ ꢈꢁꢓ ꢁꢔ ꢕ ꢓꢋꢉ

SCLS558 − JANUARY 2004

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

Outputs Can Drive Up To 10 LSTTL Loads

Low Power Consumption, 20-µA Max I

Typical t = 9 ns

4-mA Output Drive at 5 V

Extended Temperature Performance of

−40°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Low Input Current of 1 µA Max

D OR PW PACKAGE

(TOP VIEW)

Enhanced Product-Change Notification

†

Qualification Pedigree

Wide Operating Voltage Range of 2 V to 6 V

13 1C

12 1Y

11 3C

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

GND

description/ordering information

The SN74HC10 device contains three independent 3-input NAND gates. It performs the Boolean function

Y = A • B • C or Y = A + B + C in positive logic.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

‡

PACKAGE

SOIC − D

Tape and reel

SN74HC10QDREP

SHC10EP

−40°C to 125°C

TSSOP − PW

SN74HC10QPWREP

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

logic diagram (positive logic)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢊ

ꢌ

ꢑ

ꢔ

ꢐ

ꢅ

ꢋ

ꢍ

ꢑ

ꢁ

ꢔ

ꢓ

ꢋ

ꢓ

ꢖ

ꢗ

ꢘ

ꢙ

ꢚ

ꢛ

ꢜ

ꢝ

ꢖ

ꢙ

ꢗ

ꢖ

ꢞ

ꢟ

ꢠ

ꢚ

ꢡ

ꢗ

ꢝ

ꢜ

ꢞ

ꢙ

ꢘ

ꢢ

ꢠ

ꢣ

ꢤ

ꢖ

ꢟ

ꢜ

ꢝ

ꢖ

ꢙ

ꢗ

ꢥ

ꢜ

ꢝ

ꢡ

ꢦ

ꢊꢚ ꢙ ꢥꢠꢟ ꢝ ꢞ ꢟ ꢙꢗ ꢘꢙ ꢚ ꢛ ꢝ ꢙ ꢞ ꢢꢡ ꢟ ꢖꢘ ꢖꢟꢜ ꢝꢖ ꢙꢗꢞ ꢢꢡ ꢚ ꢝꢧ ꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢋꢡꢨ ꢜꢞ ꢍꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ

ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢩ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢪꢦ ꢊꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢫ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ

ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

中文翻译

下载PDF

SN74HC10QPWREP 替代型号

型号	品牌	替代类型	描述	数据表
SN74HC10QPWRQ1	TI	完全替代	TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74HC10PWR	TI	类似代替	TRIPLE 3-INPUT POSITIVE-NAND GATES
SN74HC10PW	TI	类似代替	TRIPLE 3-INPUT POSITIVE-NAND GATES

与SN74HC10QPWREP相关器件

型号	品牌	获取价格	描述	数据表
SN74HC10QPWRG4Q1	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74HC10QPWRQ1	TI	获取价格	TRIPLE 3-INPUT POSITIVE-NAND GATE
SN74HC11	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN74HC11_07	TI	获取价格	TRIPLE 3-INPUT POSITIVE-AND GATES
SN74HC112	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC112D	TI	获取价格	DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
SN74HC112D-00	TI	获取价格	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
SN74HC112D3	TI	获取价格	暂无描述
SN74HC112DG4	TI	获取价格	Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85
SN74HC112DR	TI	获取价格	DUAL J-NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

与SN74HC10QPWREP相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

4
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

2
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

23
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

24

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74HC10QPWREP

SN74HC10QPWREP 数据手册

SN74HC10QPWREP 替代型号

与SN74HC10QPWREP相关器件

与SN74HC10QPWREP相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74HC10QPWREP

SN74HC10QPWREP 数据手册

SN74HC10QPWREP 替代型号

与SN74HC10QPWREP相关器件

与SN74HC10QPWREP相关文章

您还可以找

您在本页遇到什么问题？