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SN74GTL16616

更新时间： 2024-09-15 22:53:35
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德州仪器 - TI 总线收发器输出元件时钟
页数 文件大小 规格书
11页 177K
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17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS

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SN74GTL16616 数据手册

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SN54GTL16616, SN74GTL16616  
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS  
WITH BUFFERED CLOCK OUTPUTS  
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999  
SN54GTL16616 . . . WD PACKAGE  
SN74GTL16616 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
Universal Bus Transceiver (UBT  
)
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
OEAB  
LEAB  
A1  
GND  
A2  
A3  
(3.3 V)  
A4  
CEAB  
CLKAB  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
GTL Buffered CLKAB Signal (CLKOUT)  
Translate Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
B3  
V
V
(5 V)  
CC  
CC  
Support Mixed-Mode (3.3 V and 5 V) Signal  
Operation on A-Port and Control Inputs  
B4  
B5  
A5  
Equivalent to ’16601 Function  
A6 10  
47 B6  
I
Supports Partial-Power-Down Mode  
off  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
Operation  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors on A Port  
A8 13  
A9 14  
44 B8  
43 B9  
A10 15  
A11 16  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
(3.3 V) 22  
A16 23  
A17 24  
GND 25  
CLKIN 26  
OEBA 27  
LEBA 28  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND-Pin Configuration  
CC  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Ceramic Flat  
(WD) Packages  
V
35  
V
CC  
REF  
34 B16  
33 B17  
32 GND  
31 CLKOUT  
30 CLKBA  
29 CEBA  
description  
The ’GTL16616 devices are 17-bit universal  
bus transceivers (UBTs) that provide  
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL  
signal-level translation. They combine D-type  
flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data  
transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal  
levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an  
interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels.  
Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and  
output edge control (OEC ).  
The user has the flexibility of using this device at either GTL (V = 1.2 V and V  
= 0.8 V) or the preferred  
TT  
REF  
higher noise margin GTL+ (V = 1.5 V and V  
= 1 V) signal levels. GTL+ is the Texas Instruments derivative  
TT  
REF  
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or  
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V  
tolerant. V  
isthereferenceinputvoltagefortheBport. V (5V)suppliestheinternalandGTLcircuitrywhile  
REF  
CC  
V
(3.3 V) supplies the LVTTL output buffers.  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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