5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74GTL16612ADLR
SN74GTL16612ADLR PDF预览

SN74GTL16612ADLR

更新时间： 2024-11-05 22:53:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路电视光电二极管信息通信管理
页数 文件大小 规格书
15页 256K
描述
18-BIT LVTTL-TO-GTL UNIVERSAL BUS TRANSCEIVERS

阅读下载

中文翻译

获取价格

SN74GTL16612ADLR 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：PLASTIC, SSOP-56针数：56
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.73
Is Samacsys：N其他特性：ALSO REQUIRES 5V SUPPLY
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：GTL/TVCJESD-30 代码：R-PDSO-G56
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.064 A位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN/3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP56,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3,5 V传播延迟（tpd）：7.8 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTL & LVTTL
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74GTL16612ADLR 数据手册

 浏览型号SN74GTL16612ADLR的Datasheet PDF文件第2页浏览型号SN74GTL16612ADLR的Datasheet PDF文件第3页浏览型号SN74GTL16612ADLR的Datasheet PDF文件第4页浏览型号SN74GTL16612ADLR的Datasheet PDF文件第5页浏览型号SN74GTL16612ADLR的Datasheet PDF文件第6页浏览型号SN74GTL16612ADLR的Datasheet PDF文件第7页 
SN54GTL16612A, SN74GTL16612A  
18-BIT LVTTL-TO-GTL+ UNIVERSAL BUS TRANSCEIVERS  
www.ti.com  
SCES187D–JANUARY 1999–REVISED JULY 2005  
FEATURES  
•
•
•
Bus Hold on A-Port Inputs Eliminates the  
Need for External Pullup/Pulldown Resistors  
•
Members of the Texas Instruments Widebus™  
Family  
Distributed VCC and GND-Pin Configuration  
Minimizes High-Speed Switching Noise  
•
Universal Bus Transceiver (UBT™) Combines  
D-Type Latches and D-Type Flip-Flops for  
Operation in Transparent, Latched, Clocked,  
or Clock-Enabled Modes  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
•
•
Translate Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
– 1000-V Charged-Device Model (C101)  
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Support Mixed-Mode (3.3-V and 5-V) Signal  
Operation on A-Port and Control Inputs  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink Small-Outline  
(DGG), and Ceramic Flat (WD) Packages  
xxx  
B-Port Transition Time Optimized for  
Distributed Backplane Loads  
Ioff Supports Partial-Power-Down Mode  
Operation  
DESCRIPTION  
The 'GTL16612A devices are 18-bit universal bus transceivers (UBT) that provide LVTTL-to-GTL+ and  
GTL+-to-LVTTL signal-level translation. They allow for transparent, latched, clocked, or clock-enabled modes of  
data transfer. These devices provide a high-speed interface between cards operating at LVTTL logic levels and  
backplanes operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL)  
backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and  
output edge control (OEC™). Improved GTL+ OEC circuits minimize bus settling time and have been designed  
and tested using several backplane models.  
Figure 1 shows actual device output waveforms using a synchronous clock at 75 MHz. The test backplane is a  
16-slot, 14-inch board with loaded impedance of 33 Ω. VTT is 1.5 V, VREF is 1 V, and RTT pullup resistor is 50 Ω.  
The driver is in slot 8, with receivers in alternate slots 1, 3, 5, 7, 10, 12, 14, and 16. Receiver slot-1 signals are  
shown. The signal becomes progressively worse as the receiver moves closer to the driver or the spacing  
between receiver cards is reduced. The clock is independent of the data, and the system clock frequency is  
limited by the backplane flight time to about 80-90 MHz. This frequency can be increased even more (30% to  
40%) if the clock is generated and transmitted together with the data from the driver card (source synchronous).  
V
TT  
V
TT  
1.8  
TI GTL16612  
0.25”  
0.25”  
0.875”  
0.625”  
1.6  
1.4  
1.2  
Fairchild GTLP16612  
0.625”  
0.625”  
Conn.  
0.625”  
Conn.  
Conn.  
Conn.  
1.0  
0.8  
0.6  
0.4  
TI GTL16612A  
1”  
1”  
1”  
1”  
Rcvr  
Rcvr  
Rcvr  
Drvr  
Slot 8  
0
10  
20  
30  
t − Time − ns  
Slot 1  
Slot 2  
Slot 16  
Figure 1. Test Backplane Model With Output Waveform Results  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1999–2005, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are  
tested unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
1234567...15

中文翻译

下载PDF

与SN74GTL16612ADLR相关器件

型号 品牌 获取价格 描述 数据表
SN74GTL16612DGG TI

获取价格

 		18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612DGGE4 TI

获取价格

 		GTL/TVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74GTL16612DGGR TI

获取价格

 		18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612DL TI

获取价格

 		18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
SN74GTL16612DLR TI

获取价格

 		18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS
SN74GTL16615DGGR TI

获取价格

 		GTL/TVC SERIES, 17-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74GTL16615DL TI

获取价格

 		GTL/TVC SERIES, 17-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74GTL16615DLR TI

获取价格

 		GTL/TVC SERIES, 17-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74GTL16616 TI

获取价格

 		17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS
SN74GTL16616_06 TI

获取价格

 		17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS

与SN74GTL16612ADLR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证