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SN74GTL16612

更新时间： 2024-11-08 22:16:03
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德州仪器 - TI 总线收发器
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13页 188K
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18-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS

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SN74GTL16612 数据手册

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SN54GTL16612, SN74GTL16612  
18-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS  
www.ti.com  
SCBS480K–JUNE 1994–REVISED JULY 2005  
FEATURES  
SN54GTL16612. . . WD PACKAGE  
•
Members of Texas Instruments Widebus™  
Family  
SN74GTL16612. . . DGG OR DL PACKAGE  
(TOP VIEW)  
•
UBT™ Transceivers Combine D-Type Latches  
and D-Type Flip-Flops for Operation in  
Transparent, Latched, Clocked, or  
Clock-Enabled Modes  
OEAB  
LEAB  
A1  
GND  
A2  
A3  
(3.3 V)  
A4  
CEAB  
CLKAB  
1
2
3
4
5
6
7
8
9
56  
55  
54 B1  
GND  
53  
52  
51  
50  
•
•
•
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
B2  
B3  
V
Translate Between GTL/GTL+ Signal Levels  
and LVTTL Logic Levels  
V
CC  
(5 V)  
CC  
49 B4  
48 B5  
47 B6  
Support Mixed-Mode (3.3 V and 5 V) Signal  
Operation on A-Port and Control Inputs  
A5  
A6 10  
•
•
Identical to '16601 Function  
GND  
A7  
A8  
GND  
B7  
B8  
11  
12  
13  
46  
45  
44  
Ioff Supports Partial-Power-Down Mode  
Operation  
A9 14  
A10 15  
A11 16  
A12 17  
43 B9  
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors on  
A Port  
42 B10  
41 B11  
40 B12  
•
•
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
GND  
GND  
18  
39  
A13 19  
A14 20  
38 B13  
37 B14  
36 B15  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
A15 21  
V
CC  
(3.3 V) 22  
A16 23  
35  
V
REF  
34 B16  
A17 24  
33 B17  
GND 25  
A18 26  
32 GND  
31 B18  
OEBA 27  
LEBA 28  
30 CLKBA  
29 CEBA  
DESCRIPTION/ORDERING INFORMATION  
The 'GTL16612 devices are 18-bit UBT™ transceivers that provide LVTTL-to-GTL/GTL+ and  
GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for  
transparent, latched, clocked, and clock-enabled modes of data transfer identical to the '16601 function. The  
devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at  
GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced  
input threshold levels, and OEC™ circuitry.  
The user has the flexibility of using these devices at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred  
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative  
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or  
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V  
tolerant. VREF is the reference input voltage for the B port.  
VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, UBT, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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