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SN74F574NSR PDF预览

SN74F574NSR

更新时间: 2024-11-25 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
5页 72K
描述
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SO 0 to 70

SN74F574NSR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.23控制类型:INDEPENDENT CONTROL
计数方向:UNIDIRECTIONAL系列:F/FAST
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):86 mAProp。Delay @ Nom-Sup:10 ns
传播延迟(tpd):10 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
触发器类型:POSITIVE EDGE宽度:5.3 mm
Base Number Matches:1

SN74F574NSR 数据手册

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SN74F574  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SDFS005A – D3034, SEPTEMBER 1987 – REVISED OCTOBER 1993  
DW OR N PACKAGE  
(TOP VIEW)  
Eight D-Type Flip-Flops in a Single  
Package  
3-State Bus-Driving True Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description  
This 8-bit flip-flop features 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. It is particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
GND 10  
11 CLK  
The eight flip-flops of the SN74F574 are edge-triggered D-type flip-flops. On the positive transition of the clock  
(CLK) input, the Q outputs will be set to the logic levels that were set up at the data (D) inputs.  
A buffered output enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
The output enable (OE) does not affect the internal operations of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN74F574 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
X
X
X
Q
0
H
Z
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74F574NSR 替代型号

型号 品牌 替代类型 描述 数据表
54F574DMQB TI

完全替代

F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
SN74F574DWG4 TI

完全替代

Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC 0 to 70
SN74F574DWR TI

完全替代

暂无描述

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