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SN74F543DWR PDF预览

SN74F543DWR

更新时间: 2024-11-27 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
7页 99K
描述
Octal Registered Transceiver With 3-State Outputs 24-SOIC 0 to 70

SN74F543DWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP24,.4针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.14其他特性:IOL = 24MA @ VOL = 0.5V FOR PORT A; IOH = 3MA @ VOH = 2.4V FOR PORT A
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:F/FASTJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:15.4 mm
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP24,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):0.125 mAProp。Delay @ Nom-Sup:8.5 ns
传播延迟(tpd):12.5 ns认证状态:Not Qualified
施密特触发器:No座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

SN74F543DWR 数据手册

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SN74F543  
OCTAL REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SDFS025B – D2942, MARCH 1987 – REVISED OCTOBER 1993  
DB, DW, OR NT PACKAGE  
(TOP VIEW)  
3-State True Outputs  
Back-to-Back Registers for Storage  
Package Options Include Plastic  
Small-Outline and Shrink Small-Outline  
Packages and Standard Plastic 300-mil  
DIPs  
LEBA  
OEBA  
A1  
1
24  
V
CC  
2
23 CEBA  
22 B1  
21 B2  
20 B3  
19 B4  
18 B5  
17 B6  
16 B7  
3
A2  
A3  
A4  
A5  
A6  
A7  
A8  
4
5
description  
6
7
The SN74F543 octal transceiver contains two  
sets of D-type latches for temporary storage of  
data flowing in either direction. Separate  
latch-enable (LEAB or LEBA) and output enable  
(OEAB or OEBA) inputs are provided for each  
register to permit independent control in either  
direction of data flow. The A outputs are  
characterized to sink 24 mA while the B outputs  
are characterized to sink 64 mA.  
8
9
10  
11  
12  
15  
B8  
14 LEAB  
13 OEAB  
CEAB  
GND  
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. Having CEAB  
low and LEAB low makes the A-to-B latches transparent; a subsequent low-to-high transition of LEAB puts the  
A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the  
data present at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA,  
and OEBA inputs.  
The SN74F543 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN74F543 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
B
CEAB  
LEAB  
OEAB  
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
B
0
L
L
L
L
H
H
A-to-B data flow is shown; B-to-A flow control is the  
same except that it uses CEBA, LEBA, and OEBA.  
Output level before the indicated steady-state input  
conditions were established.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74F543DWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74F543DBR TI

完全替代

具有三态输出的八路寄存收发器 | DB | 24 | 0 to 70
SN74F543DW TI

完全替代

OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74F543NT TI

类似代替

OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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