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SN74F38DR PDF预览

SN74F38DR

更新时间: 2024-11-28 11:08:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器栅极
页数 文件大小 规格书
5页 71K
描述
具有集电极开路输出的 4 通道、2 输入、4.5V 至 5.5V 双极与非门 | D | 14 | 0 to 70

SN74F38DR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.82其他特性:IOL = 64MA @ VOL = 0.5V
系列:F/FASTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.064 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出特性:OPEN-COLLECTOR
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):30 mAProp。Delay @ Nom-Sup:13 ns
传播延迟(tpd):5.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.91 mmBase Number Matches:1

SN74F38DR 数据手册

 浏览型号SN74F38DR的Datasheet PDF文件第2页浏览型号SN74F38DR的Datasheet PDF文件第3页浏览型号SN74F38DR的Datasheet PDF文件第4页浏览型号SN74F38DR的Datasheet PDF文件第5页 
SN54F38, SN74F38  
QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS  
WITH OPEN-COLLECTOR OUTPUTS  
SDFS013A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F38 . . . J PACKAGE  
SN74F38 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
1Y  
2A  
These devices contain four independent 2-input  
NAND buffer gates with open-collector outputs.  
They perform the Boolean functions Y = A B or  
Y = A + B in positive logic.  
2B  
2Y  
GND  
8
The open-collector outputs require pullup  
resistors to perform correctly. They may be  
connected to other open-collector outputs to  
implement active-low wired-OR or active-high  
wired-AND functions. Open-collector devices are  
SN54F38 . . . FK PACKAGE  
(TOP VIEW)  
often used to generate higher V  
levels.  
OH  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4A  
NC  
4Y  
NC  
3B  
4
5
6
7
8
The SN54F38 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F38 is characterized for  
operation from 0°C to 70°C.  
17  
16  
15  
14  
NC  
2B  
9 10 11 12 13  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
NC – No internal connection  
H
L
L
H
H
X
logic symbol  
logic diagram (positive logic)  
1
1A  
2
1
&
3
6
1A  
2
3
6
8
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
4
1B  
4
2A  
5
2A  
5
2B  
9
2B  
9
3A  
3A  
10  
3B  
12  
4A  
13  
4B  
8
10  
3B  
11  
12  
4A  
11  
13  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74F38DR 替代型号

型号 品牌 替代类型 描述 数据表
SN74F38D TI

完全替代

QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS
SN74F00DR TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SN74F00D TI

类似代替

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

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