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ꢇ ꢈꢉꢊ ꢋꢌ ꢍꢁꢊ ꢎꢏꢐ ꢀꢑꢒꢌꢀ ꢓꢊꢄ ꢋꢈꢀꢋꢔ ꢐꢑꢕ ꢏꢌ ꢐꢏ ꢕ ꢊꢀ ꢋꢏ ꢐ
ꢖ ꢊꢋ ꢓꢌ ꢀꢗꢁꢘ ꢓꢐꢔ ꢁꢔ ꢍꢀꢌ ꢘꢒ ꢏꢑꢐ ꢌꢑꢁꢙ ꢌꢅ ꢈꢀꢋꢑꢋ ꢏꢌ ꢔ ꢍꢋ ꢚꢍ ꢋꢀ
SDFS072A − D2932, MARCH 1987 − REVISED OCTOBER 1993
DW OR N PACKAGE
(TOP VIEW)
• Four Modes of Operation:
Hold (Store)
Shift Right
Shift Left
Load Data
S0
OE1
OE2
V
CC
19 S1
1
2
3
4
5
6
7
8
9
10
20
18 SL
• Operates With Outputs Enabled or at High
17
16
15
14
13
12
11
G/Q
Q
H′
G
Impedance
E/Q
H/Q
E
H
• 3-State Outputs Drive Bus Lines Directly
• Can Be Cascaded for N-Bit Word Lengths
• Synchronous Clear
C/Q
F/Q
C
F
A/Q
Q
D/Q
B/Q
A
D
A′
B
CLR
GND
CLK
SR
• Applications:
Stacked or Push-Down Registers
Buffer Storage
Accumulator Registers
• Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This 8-bit universal register features multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin
package. Two function-select (S0, S1) and two output-enable (OE1, OE2) inputs can be used to choose the
modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs
in a high-impedance state and permits data that is applied on the I/O ports to be clocked into the register.
Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs
synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but this
has no effect on clearing, shifting, or storage of data.
The SN74F323 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
I/O PORTS
OUTPUTS
MODE
Clear
Hold
†
†
CLR S1 S0 OE1
OE2
CLK SL SR A/Q
B/Q
L
C/Q
L
D/Q
E/Q
L
F/Q
L
G/Q
L
H/Q
L
Q
Q
A
B
C
D
E
F
G
H
A′
H′
L
L
X
L
L
X
H
L
L
L
X
L
L
L
L
L
L
X
L
↑
↑
↑
X
L
↑
↑
↑
↑
↑
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
L
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
H0
Q
H0
Q
Gn
Q
Gn
A0
A0
B0
C0
D0
D0
Cn
Cn
En
En
E0
F0
G0
G0
H0
A0
A0
X
L
X
H
H
L
L
Q
Q
Q
Q
Q
Q
Q
B0
An
An
Cn
Cn
C0
Bn
Bn
Dn
E0
Dn
Dn
F0
En
En
Gn
H0
Gn
Gn
L
H
L
Q
Q
H
L
Shift
Right
Fn
Fn
Hn
L
L
H
H
H
L
X
X
X
Q
Q
Q
Q
Q
Q
Q
H
L
h
Q
H
L
h
Shift
Left
Bn
Bn
Fn
Fn
Bn
Bn
L
L
Q
Q
Dn
c
Gn
f
Hn
g
Load
H
X
X
a
b
d
e
a
NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. These data inputs are loaded into the flip-flops while the
flip-flop outputs are isolated from the I/O terminals.
†
When one or both output-enable inputs are high the eight I/O terminals are disabled to the high-impedance state; however, sequential operation
or clearing of the register is not affected.
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Copyright 1993, Texas Instruments Incorporated
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