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SN74F240DBRE4 PDF预览

SN74F240DBRE4

更新时间: 2024-10-31 12:04:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
18页 1049K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SN74F240DBRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:GREEN, PLASTIC, SSOP-20针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.69Is Samacsys:N
控制类型:ENABLE LOW系列:F/FAST
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:7.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:1位数:4
功能数量:2端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):75 mA
Prop。Delay @ Nom-Sup:8 ns传播延迟(tpd):8 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

SN74F240DBRE4 数据手册

 浏览型号SN74F240DBRE4的Datasheet PDF文件第2页浏览型号SN74F240DBRE4的Datasheet PDF文件第3页浏览型号SN74F240DBRE4的Datasheet PDF文件第4页浏览型号SN74F240DBRE4的Datasheet PDF文件第5页浏览型号SN74F240DBRE4的Datasheet PDF文件第6页浏览型号SN74F240DBRE4的Datasheet PDF文件第7页 
SN54F240, SN74F240  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SDFS061A – D2932, MARCH 1987 – REVISED OCTOBER 1993  
SN54F240 . . . J PACKAGE  
SN74F240 . . . DB, DW, OR N PACKAGE  
(TOP VIEW)  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
Package Options Include Plastic  
Small-Outline (SOIC) and Shrink  
Small-Outline (SSOP) Packages, Ceramic  
Chip Carriers, and Plastic and Ceramic  
DIPs  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
description  
These octal buffers and line drivers are designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters. Taken together with the F241 and  
F244, these devices provide the choice of  
selected combinations of inverting and  
noninverting outputs, symmetrical OE (active-low  
output-enable) inputs, and complementary OE  
and OE inputs.  
13 2A2  
12 1Y4  
11  
2A1  
SN54F240 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
The F240 is organized as two 4-bit buffers/line  
drivers with separate output enable (OE) inputs.  
When OE is low, the device passes data from the  
A inputs to the Y outputs. When OE is high, the  
outputs are in the high-impedance state.  
17  
16  
15  
14  
9 10 11 12 13  
The SN74F240 is available in TI’s shrink  
small-outline package (DB), which provides the  
same I/O pin count and functionality of standard  
small-outline packages in less than half the  
printed-circuit-board area.  
The SN54F240 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F240 is characterized for  
operation from 0°C to 70°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
L
H
Z
H
X
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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