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SN74F2373DWG4 PDF预览

SN74F2373DWG4

更新时间： 2024-09-13 14:44:51
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
13页 463K
描述
F/FAST SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20

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SN74F2373DWG4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-20针数：20
Reach Compliance Code：compliant风险等级：5.62
Is Samacsys：N系列：F/FAST
JESD-30 代码：R-PDSO-G20长度：12.8 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.012 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：66 mAProp。Delay @ Nom-Sup：9 ns
传播延迟（tpd）：13 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

SN74F2373DWG4 数据手册

 浏览型号SN74F2373DWG4的Datasheet PDF文件第2页浏览型号SN74F2373DWG4的Datasheet PDF文件第3页浏览型号SN74F2373DWG4的Datasheet PDF文件第4页浏览型号SN74F2373DWG4的Datasheet PDF文件第5页浏览型号SN74F2373DWG4的Datasheet PDF文件第6页浏览型号SN74F2373DWG4的Datasheet PDF文件第7页 
SN74F2373  
25-Ω OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SDFS100 – JANUARY 1996  
DB, DW, OR N PACKAGE  
(TOP VIEW)  
Eight Latches in a Single Package  
3-State True Outputs With 25-Ω Sink  
Resistors  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
Full Parallel Access for Loading  
Buffered Control Inputs  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB) Packages, and Plastic (N) DIPs  
description  
13 5D  
12 5Q  
11 LE  
This 8-bit latch features 3-state outputs designed  
to sink up to 12 mA, and include 25-Ω sink resitors  
to reduce overshoot and undershoot.  
GND 10  
The eight latches of the SN74F2373 are transparent D-type latches. While the latch-enable (LE) input is high,  
the Q outputs follow the data (D) inputs. When the LE is taken low, the Q outputs are latched at the logic levels  
set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal  
logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability  
to drive bus lines without need for interface or pullup components.  
OE input does not affect the internal operations of the latches. Old data can be retained or new data can be  
entered while the outputs are in the high-impedance state.  
The SN74F373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN74F373 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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 		25-ohm OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
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SN74F240DBLE TI

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 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74F240DBR TI

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 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74F240DBRE4 TI

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SN74F240DBRG4 TI

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 		OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74F240DN TI

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