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SN74F138NSRE4 PDF预览

SN74F138NSRE4

更新时间: 2024-10-31 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 驱动输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
17页 1026K
描述
F/FAST SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, GREEN, PLASTIC, SOP-16

SN74F138NSRE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP16,.3针数:16
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
其他特性:TWO ACTIVE-LOW AND ONE ACTIVE-HIGH ENABLE INPUTS系列:F/FAST
输入调节:STANDARDJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.2 mm
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.02 A
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):20 mAProp。Delay @ Nom-Sup:9 ns
传播延迟(tpd):9 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

SN74F138NSRE4 数据手册

 浏览型号SN74F138NSRE4的Datasheet PDF文件第2页浏览型号SN74F138NSRE4的Datasheet PDF文件第3页浏览型号SN74F138NSRE4的Datasheet PDF文件第4页浏览型号SN74F138NSRE4的Datasheet PDF文件第5页浏览型号SN74F138NSRE4的Datasheet PDF文件第6页浏览型号SN74F138NSRE4的Datasheet PDF文件第7页 
SN54F138, SN74F138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SDFS051B – MARCH 1987 – REVISED JULY 1996  
SN54F138 . . . J PACKAGE  
SN74F138 . . . D OR N PACKAGE  
(TOP VIEW)  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
Incorporates Three Enable Inputs to  
Simplify Cascading and/or Data Reception  
V
A
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
CC  
Y0  
Y1  
Y2  
Y3  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
C
G2A  
G2B  
G1  
11 Y4  
10  
9
Y5  
Y6  
Y7  
description  
GND  
The F138 is designed to be used in  
high-performance memory-decoding or data-  
routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, these decoders can be used to  
minimize the effects of system decoding. When  
employed with high-speed memories utilizing a  
fast enable circuit, the delay times of this decoder  
and the enable time of the memory are usually  
less than the typical access time of the memory.  
This means that the effective system delay  
introduced by the decoder is negligible.  
SN54F138 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
C
G2A  
NC  
4
5
6
7
8
Y1  
Y2  
NC  
Y3  
Y4  
17  
16  
15  
14  
G2B  
G1  
9 10 11 12 13  
The conditions at the binary-select inputs and the  
three enable inputs select one of eight output  
lines. Two active-low and one active-high enable  
inputs reduce the need for external gates or  
inverters when expanding. A 24-line decoder can  
NC – No internal connection  
be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can  
be used as a data input for demultiplexing applications.  
The SN54F138 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74F138 is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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