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SN74F125 PDF预览

SN74F125

更新时间: 2024-11-29 22:53:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
5页 69K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74F125 数据手册

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SN74F125  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
SDFS016A – D3211, JANUARY 1989 – REVISED OCTOBER 1993  
D OR N PACKAGE  
(TOP VIEW)  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
Package Options Include Plastic  
Small-Outline Packages and Standard  
Plastic 300-mil DIPs  
1OE  
1A  
V
CC  
13 4OE  
12 4A  
1
2
3
4
5
6
7
14  
1Y  
11  
10  
9
2OE  
2A  
4Y  
description  
3OE  
3A  
The SN74F125 features independent line drivers  
with 3-state outputs. Each output is disabled when  
the associated output enable (OE) input is high.  
2Y  
8
GND  
3Y  
TheSN74F125ischaracterizedforoperationfrom  
0°C to 70°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
H
L
OE  
A
H
L
L
L
H
X
Z
logic symbol  
logic diagram (positive logic)  
1
1
1
EN  
1OE  
3
6
1OE  
2
1Y  
2Y  
1A  
4
2
3
6
1A  
1Y  
2Y  
2OE  
5
2A  
4
10  
3OE  
9
2OE  
8
3Y  
4Y  
3A  
5
13  
2A  
11  
4OE  
12  
4A  
10  
3OE  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
9
8
3A  
3Y  
4Y  
13  
4OE  
12  
11  
4A  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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