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SN74CBTU4411 PDF预览

SN74CBTU4411

更新时间: 2024-11-02 05:17:35
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德州仪器 - TI 复用器开关输出元件双倍数据速率
页数 文件大小 规格书
15页 386K
描述
11-BIT 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 1.8-V DDR-II SWITCH WITH CHARGE PUMP AND PRECHARGED OUTPUTS

SN74CBTU4411 数据手册

 浏览型号SN74CBTU4411的Datasheet PDF文件第2页浏览型号SN74CBTU4411的Datasheet PDF文件第3页浏览型号SN74CBTU4411的Datasheet PDF文件第4页浏览型号SN74CBTU4411的Datasheet PDF文件第5页浏览型号SN74CBTU4411的Datasheet PDF文件第6页浏览型号SN74CBTU4411的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢃ ꢃꢈꢈ  
ꢈꢈ ꢉꢅꢊ ꢆ ꢈ ꢉꢋ ꢌꢉ ꢃ ꢌ ꢍꢆ ꢎ ꢇꢏꢆ ꢊꢐ ꢏꢍ ꢑꢍꢒꢓ ꢔꢍꢎ ꢇꢏꢆꢊ ꢐ ꢏꢍ ꢑꢍ ꢒ  
ꢈ ꢕ ꢖ ꢉꢗ ꢔꢔ ꢒꢉꢊ ꢊ ꢀ ꢘꢊ ꢆꢄ ꢙ ꢘ ꢊꢆ ꢙ ꢄꢙꢚ ꢒꢛ ꢍ ꢐꢇꢎ ꢐ ꢚꢁꢔ ꢐꢒꢍ ꢄꢙꢚꢒ ꢛꢍ ꢔ ꢋ ꢇꢆ ꢐꢇ ꢆꢀ  
SCDS192 − APRIL 2005  
D
D
D
D
D
D
Supports SSTL_18 Signaling Levels  
Suitable for DDR-II Applications  
D
Internal 400-W Pulldown Resistors  
D
D
D
Low Differential and Rising/Falling Edge  
Skew  
D−Port Outputs Are Precharged by Bias  
Voltage (V  
)
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
BIAS  
Internal Termination for Control Inputs  
High Bandwidth (334 MHz Min)  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
Low and Flat ON-State Resistance (r  
on  
)
Characteristics, (r = 17 W Max)  
on  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74CBTU4411 is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low  
ON-state resistance (r ). The device utilizes an internal charge pump to elevate the gate voltage of the pass  
on  
transistor, providing a low and flat r . The low and flat r allows for minimal propagation delay and supports  
on  
on  
rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to  
minimize capacitive loading and signal distortion on the data bus. Matched r and I/O capacitance among  
on  
channels results in extremely low differential and rising/falling edge skew. This allows the device to show optimal  
performance in DDR-II applications.  
The device is organized as an 11-bit 1-of-4 multiplexer/demultiplexer with a single switch-enable (EN) input.  
When EN is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the  
disabled channels are connected to V  
for the disabled D10 ports. When DQS_EN is low, this voltage is V  
D10 ports are connected to an internal voltage (V  
through a 400 resistor. DQS_EN determines the output voltage  
BIAS  
. When DQS_EN is high, the disabled  
BIAS  
) source, which is approximately equal to 0.7 V  
.
BIAS_DQS  
DD  
When EN is high, all the channels are disabled. Ports D0 to D9 are connected to V  
disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is V  
. For the D10 port, the  
BIAS  
. When  
BIAS  
DQS_EN is high, this voltage is V  
.
DD  
The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. The EN and TC inputs  
determine the internal termination for S0 and S1 inputs. When EN is low, the termination is determined by the  
TC input. When both EN and TC are low, termination resistors are disconnected from the S inputs. When EN  
is low and TC is high, both pullup and pulldown resistors are connected to the S inputs. When EN is high, only  
the pulldown termination resistors are connected to the S inputs, regardless of the voltage level at the TC input.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
PACKAGE  
LFBGA − GST  
A
0°C to 85°C  
Tape and reel  
SN74CBTU4411GSTR  
CTU4411  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢧ  
Copyright 2005, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢰ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢕ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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