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SN74CBTLV3384PWLE

更新时间： 2024-11-09 13:13:47
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SN74CBTLV3384PWLE 数据手册

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SCDS059G − MARCH 1998 − REVISED JUNE 2004  
DBQ, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
5-Ω Switch Connection Between Two Ports  
Rail-to-Rail Switching on Data I/O Ports  
I
Supports Partial-Power-Down Mode  
1OE  
1B1  
1A1  
1A2  
1B2  
1B3  
1A3  
1A4  
1B4  
1B5  
1A5  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
off  
Operation  
2B5  
2A5  
2A4  
2B4  
2B3  
2A3  
2A2  
2B2  
2
3
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
4
5
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
6
7
8
9
description/ordering information  
10  
11  
12  
15 2B1  
The SN74CBTLV3384 provides ten bits of  
high-speed bus switching. The low on-state  
resistance of the switch allows connections to be  
made with minimal propagation delay.  
2A1  
2OE  
14  
13  
The device is organized as dual 5-bit bus switches  
with separate output-enable (OE) inputs. It can be  
used as two 5-bit bus switches or one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is on,  
and A port is connected to B port. When OE is high, the switch is open, and the high-impedance state exists  
between the two ports.  
This device is fully specified for partial-power-down applications using I . The I feature ensures that  
off  
off  
damaging current will not backflow through the device when it is powered down. The device has isolation during  
power off.  
To ensure the high-impedance state during power up or power down, OE shall be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QSOP − DBQ  
SOIC − DW  
Tape and reel  
Tube  
SN74CBTLV3384DBQR  
SN74CBTLV3384DW  
SN74CBTLV3384DWR  
SN74CBTLV3384PWR  
SN74CBTLV3384DGVR  
CBTLV3384  
CBTLV3384  
−40°C to 85°C  
Tape and reel  
Tape and reel  
Tape and reel  
TSSOP − PW  
TVSOP − DGV  
CL384  
CL384  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each 5-bit bus switch)  
INPUTS  
INPUTS/OUTPUTS  
1OE  
2OE  
L
1B1−1B5  
1A1−1A5  
1A1−1A5  
Z
2B1−2B5  
2A1−2A5  
Z
L
L
H
H
H
L
2A1−2A5  
Z
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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