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SN74CBTD3384CPW PDF预览

SN74CBTD3384CPW

更新时间: 2024-11-18 23:06:19
品牌 Logo 应用领域
德州仪器 - TI 开关
页数 文件大小 规格书
16页 357K
描述
10-BIT FET BUS SWITCH WITH LEVEL SHIFTING 5-V BUS SWITCH WITH -2-V UNDERSHOOT PROTECTION

SN74CBTD3384CPW 数据手册

 浏览型号SN74CBTD3384CPW的Datasheet PDF文件第2页浏览型号SN74CBTD3384CPW的Datasheet PDF文件第3页浏览型号SN74CBTD3384CPW的Datasheet PDF文件第4页浏览型号SN74CBTD3384CPW的Datasheet PDF文件第5页浏览型号SN74CBTD3384CPW的Datasheet PDF文件第6页浏览型号SN74CBTD3384CPW的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢈ ꢉꢃ ꢄ  
ꢊ ꢋ ꢌꢅꢍ ꢆ ꢎ ꢏꢆ ꢅꢐꢀ ꢀꢑ ꢍ ꢆꢄ ꢒ ꢑ ꢍꢆ ꢒ ꢓ ꢏꢔꢏ ꢓ ꢀ ꢒꢍ ꢎꢆ ꢍꢁ ꢕ  
ꢖ ꢌꢔ ꢅꢐꢀ ꢀꢑ ꢍ ꢆꢄ ꢒ ꢑ ꢍꢆ ꢒ ꢗ ꢘ ꢌꢔ ꢐꢁꢇ ꢏꢙꢀꢒ ꢚꢚ ꢆ ꢛꢙꢚ ꢆ ꢏꢄ ꢆꢍ ꢚ ꢁ  
SCDS133A −SEPTEMBER 2003 − REVISED OCTOBER 2003  
D
D
D
D
D
Undershoot Protection for Off-Isolation on  
A and B Ports Up To −2 V  
D
D
D
D
D
Data I/Os Support 0 to 5-V Signaling Levels  
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)  
Integrated Diode to V  
Down To 3.3-V Output Level Shift  
Provides 5-V Input  
Control Inputs Can be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
CC  
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Low ON-State Resistance (r  
)
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
on  
Characteristics (r = 3 Typical)  
on  
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
(C  
= 5 pF Typical)  
io(OFF)  
− 1000-V Charged-Device Model (C101)  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
D
Supports Both Digital and Analog  
Applications: Memory Interleaving, Bus  
Isolation, Low-Distortion Signal Gating  
V
Operating Range From 4.5 V to 5.5 V  
CC  
DB, DBQ, DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1OE  
1B1  
1A1  
1A2  
1B2  
1B3  
1A3  
1A4  
1B4  
1B5  
1A5  
GND  
V
CC  
2
2B5  
2A5  
2A4  
2B4  
2B3  
2A3  
2A2  
2B2  
2B1  
2A1  
2OE  
3
4
5
6
7
8
9
10  
11  
12  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74CBTD3384CDW  
SN74CBTD3384CDWR  
SN74CBTD3384CDB  
SN74CBTD3384CDBR  
SN74CBTD3384CDBQR  
SN74CBTD3384CPW  
SN74CBTD3384CPWR  
SN74CBTD3384CDGVR  
SOIC − DW  
SSOP − DB  
CBTD3384C  
Tape and reel  
Tube  
CC384C  
Tape and reel  
−40°C to 85°C  
SSOP (QSOP) − DBQ Tape and reel  
CBTD3384C  
Tube  
TSSOP − PW  
Tape and reel  
CC384C  
CC384C  
TVSOP − DGV  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢨ  
Copyright 2003, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74CBTD3384CPW 替代型号

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