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SN74CBTD3306PWLE PDF预览

SN74CBTD3306PWLE

更新时间: 2024-11-26 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器开关逻辑集成电路光电二极管
页数 文件大小 规格书
12页 755K
描述
DUAL FET BUS SWITCH WITH LEVEL SHIFTING

SN74CBTD3306PWLE 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:PLASTIC, TSSOP-8针数:8
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.07Is Samacsys:N
其他特性:BUS SWITCH系列:CBT/FST/QS/5C/B
JESD-30 代码:R-PDSO-G8长度:4.4 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:1功能数量:2
端口数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):0.25 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

SN74CBTD3306PWLE 数据手册

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SN74CBTD3306  
DUAL FET BUS SWITCH  
WITH LEVEL SHIFTING  
SCDS030L − JANUARY 1996 − REVISED JANUARY 2004  
D OR PW PACKAGE  
(TOP VIEW)  
D
D
D
5-Ω Switch Connection Between Two Ports  
TTL-Compatible Input Levels  
Designed to Be Used in Level-Shifting  
Applications  
1OE  
1A  
VCC  
2OE  
2B  
1
2
3
4
8
7
6
5
1B  
description/ordering information  
2A  
GND  
The SN74CBTD3306 features two independent  
line switches. Each switch is disabled when the  
associated output-enable (OE) input is high. A  
diode to V is integrated on the chip to allow for  
CC  
level shifting from 5-V signals at the device inputs  
to 3.3-V signals at the device outputs.  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
T
PACKAGE  
A
PART NUMBER  
SN74CBTD3306D  
SN74CBTD3306DR  
SN74CBTD3306PW  
SN74CBTD3306PWR  
Tube  
SOIC − D  
CC306  
CC306  
Tape and reel  
Tube  
−40°C to 85°C  
TSSOP − PW  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each bus switch)  
INPUT  
FUNCTION  
OE  
L
A port = B port  
Disconnect  
H
logic diagram (positive logic)  
2
1
3
6
1B  
2B  
1A  
1OE  
5
7
2A  
2OE  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright © 2004, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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