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SN74CBT3125 PDF预览

SN74CBT3125

更新时间: 2024-01-19 20:16:07
品牌 Logo 应用领域
德州仪器 - TI 开关
页数 文件大小 规格书
4页 67K
描述
QUADRUPLE FET BUS SWITCH

SN74CBT3125 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFN
包装说明:HVQCCN, LCC14/18,.14SQ,20针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.38
Is Samacsys:N控制类型:ENABLE LOW
计数方向:BIDIRECTIONAL系列:CBT/FST/QS/5C/B
JESD-30 代码:S-PQCC-N14JESD-609代码:e4
长度:3.5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER湿度敏感等级:2
位数:4功能数量:1
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC14/18,.14SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):0.003 mAProp。Delay @ Nom-Sup:0.25 ns
传播延迟(tpd):0.35 ns认证状态:Not Qualified
座面最大高度:1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.5 mm
Base Number Matches:1

SN74CBT3125 数据手册

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SN74CBT3125  
QUADRUPLE FET BUS SWITCH  
SCDS021E – MAY 1995 – REVISED MAY 1998  
D, DB, DGV, OR PW PACKAGE  
(TOP VIEW)  
Standard ’125-Type Pinout  
5-Switch Connection Between Two Ports  
TTL-Compatible Input Levels  
1OE  
1A  
V
CC  
1
2
3
4
5
6
7
14  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB, DBQ), Thin Very Small-Outline (DGV),  
and Thin Shrink Small-Outline (PW)  
Packages  
13 4OE  
12 4A  
11 4B  
1B  
2OE  
2A  
2B  
10  
9
3OE  
3A  
8
GND  
3B  
description  
The SN74CBT3125 quadruple FET bus switch  
features independent line switches. Each switch  
is disabled when the associated output-enable  
(OE) input is high.  
DBQ PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
4OE  
4A  
4B  
3OE  
3A  
NC  
1OE  
1A  
1B  
2OE  
2A  
CC  
The SN74CBT3125 is characterized for operation  
from –40°C to 85°C.  
FUNCTION TABLE  
(each bus switch)  
3B  
NC  
2B  
GND  
INPUT  
FUNCTION  
OE  
L
A port = B port  
Disconnect  
NC – No internal connection  
H
logic diagram (positive logic)  
2
3
6
1A  
1B  
1
5
1OE  
2A  
2B  
3B  
4B  
4
2OE  
3A  
9
8
10  
12  
3OE  
4A  
11  
13  
4OE  
Pin numbers shown are for the D, DB, DGV, and PW packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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