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SN74CBT16244CDLR PDF预览

SN74CBT16244CDLR

更新时间: 2024-12-01 05:17:35
品牌 Logo 应用领域
德州仪器 - TI 开关
页数 文件大小 规格书
11页 188K
描述
16-BIT FET BUS SWITCH 5-V BUS SWITCH WITH-2-V UNDERSHOOT PROTECTION

SN74CBT16244CDLR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.68控制类型:ENABLE LOW
计数方向:BIDIRECTIONAL系列:CBT/FST/QS/5C/B
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:15.88 mm逻辑集成电路类型:BUS DRIVER
湿度敏感等级:1位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.003 mA
Prop。Delay @ Nom-Sup:0.15 ns传播延迟(tpd):0.24 ns
认证状态:Not Qualified座面最大高度:2.79 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.49 mm
Base Number Matches:1

SN74CBT16244CDLR 数据手册

 浏览型号SN74CBT16244CDLR的Datasheet PDF文件第2页浏览型号SN74CBT16244CDLR的Datasheet PDF文件第3页浏览型号SN74CBT16244CDLR的Datasheet PDF文件第4页浏览型号SN74CBT16244CDLR的Datasheet PDF文件第5页浏览型号SN74CBT16244CDLR的Datasheet PDF文件第6页浏览型号SN74CBT16244CDLR的Datasheet PDF文件第7页 
ꢇ ꢈ ꢊꢅꢋ ꢆ ꢌ ꢍꢆ ꢅꢎꢀ ꢀ ꢏꢋ ꢆꢄ  
SCDS134A − SEPTEMBER 2003 − REVISED OCTOBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
WidebusFamily  
Undershoot Protection for Off-Isolation on  
A and B Ports Up To −2 V  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1B1  
1B2  
GND  
1B3  
1B4  
2OE  
1A1  
1A2  
GND  
1A3  
1A4  
2
Bidirectional Data Flow, With Near-Zero  
Propagation Delay  
3
4
Low ON-State Resistance (r  
)
5
on  
Characteristics (r = 3 Typical)  
6
on  
7
V
V
Low Input/Output Capacitance Minimizes  
Loading and Signal Distortion  
CC  
CC  
8
2B1  
2B2  
GND  
2B3  
2B4  
3B1  
3B2  
GND  
3B3  
3B4  
2A1  
2A2  
GND  
2A3  
2A4  
3A1  
3A2  
GND  
3A3  
3A4  
9
(C  
= 5.5 pF Typical)  
io(OFF)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
D
Data and Control Inputs Provide  
Undershoot Clamp Diodes  
Low Power Consumption  
(I  
= 3 µA Max)  
CC  
D
V
Operating Range From 4 V to 5.5 V  
CC  
D
Data I/Os Support 0 to 5-V Signaling Levels  
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)  
V
V
D
D
D
D
Control Inputs Can Be Driven by TTL or  
5-V/3.3-V CMOS Outputs  
CC  
CC  
4B1  
4B2  
GND  
4B3  
4B4  
4A1  
4A2  
GND  
4A3  
4A4  
3OE  
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
4OE  
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 1000-V Charged-Device Model (C101)  
D
Supports Both Digital and Analog  
Applications: PCI Interface, Memory  
Interleaving, Bus Isolation, Low-Distortion  
Signal Gating  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74CBT16244CDL  
SSOP − DL  
CBT16244C  
Tape and reel  
Tube  
SN74CBT16244CDLR  
SN74CBT16244CDGG  
SN74CBT16244CDGGR  
SN74CBT16244CDGVR  
−40°C to 85°C  
TSSOP − DGG  
TVSOP − DGV  
CBT16244C  
CY244C  
Tape and reel  
Tape and reel  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢆꢤ  
Copyright 2003, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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