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SN74BCT651DW

更新时间： 2024-11-24 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 236K
描述
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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SN74BCT651DW 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP24,.4针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.88其他特性：SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：BCT/FBTJESD-30 代码：R-PDSO-G24
长度：15.4 mm负载电容（CL）：50 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.064 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：62 mA
Prop。Delay @ Nom-Sup：12.6 ns传播延迟（tpd）：11.8 ns
认证状态：Not Qualified座面最大高度：2.65 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.5 mm

SN74BCT651DW 数据手册

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SCBS054A − AUGUST 1990 − REVISED NOVEMBER 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
• State-of-the-Art BiCMOS Design  
Significantly Reduces I  
CCZ  
• Independent Registers for A and B Buses  
• Multiplexed Real-Time and Stored Data  
• Inverting Data Paths  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
1
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8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
CLKBA  
SBA  
OEBA  
B1  
B2  
B3  
• Power-Up High-Impedance Mode  
A2  
A3  
A4  
A5  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
B4  
B5  
A6  
description  
A7 10  
15 B6  
This SN74BCT651 consists of bus transceiver  
circuits, D-type flip-flops, and control circuitry  
arranged for multiplexed transmission of data  
directly from the data bus or from the internal  
A8  
GND  
B7  
B8  
11  
12  
14  
13  
storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.  
The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.  
A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four  
fundamental bus-management functions that can be performed with the SN74BCT651.  
Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the  
appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and  
SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops  
by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when  
all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.  
The SN74BCT651 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
CLKAB  
DATA I/O  
A1 THRU A8  
OPERATION OR FUNCTION  
OEAB  
OEBA  
CLKBA  
SAB  
X
SBA  
X
B1 THRU B8  
Input  
L
L
H
H
H
H
X
L
H or L  
H or L  
Input  
Input  
Isolation  
↑
↑
X
X
Input  
Store A and B data  
†
X
H
L
↑
H or L  
X
X
Input  
Unspecified  
Store A, hold B  
‡
X
↑
↑
X
Input  
Output  
Input  
Store A in both registers  
Hold A, store B  
†
H or L  
↑
X
X
X
X
L
X
Unspecified  
Output  
Output  
Output  
Input  
‡
X
L
↑
X
↑
X
Input  
Store B in both registers  
Real-time B data to A bus  
Stored B data to A bus  
Real-time A data to B bus  
Stored A data to B bus  
L
L
L
H
X
X
Input  
L
L
X
H or L  
X
Input  
H
H
H
H
X
Output  
Output  
H or L  
X
H
Input  
Stored A data to B bus and  
stored B data to A bus  
H
L
H or L  
H or L  
H
H
Output  
Output  
†
‡
The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,  
i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.  
When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus  
setup and hold times. When select control is high, clocks must be staggered in order to load both registers.  
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Copyright 1993, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...10

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