SN74BCT651

更新时间： 2024-09-15 12:22:31

品牌	Logo	应用领域
德州仪器 - TI		总线收发器输出元件
页数	文件大小	规格书
10页	236K
描述
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

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中文翻译

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数据手册

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SN74BCT651 数据手册

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ꢕ ꢑꢆ ꢖꢍ ꢗ ꢘꢀꢆꢋꢆ ꢐꢍ ꢊꢎ ꢆꢙ ꢎꢆ ꢀ

SCBS054A − AUGUST 1990 − REVISED NOVEMBER 1993

DW OR NT PACKAGE

(TOP VIEW)

• State-of-the-Art BiCMOS Design

Significantly Reduces I

CCZ

• Independent Registers for A and B Buses

• Multiplexed Real-Time and Stored Data

• Inverting Data Paths

CLKAB

SAB

OEAB

CLKBA

SBA

OEBA

• Power-Up High-Impedance Mode

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic 300-mil DIPs (NT)

description

A7 10

15 B6

This SN74BCT651 consists of bus transceiver

circuits, D-type flip-flops, and control circuitry

arranged for multiplexed transmission of data

directly from the data bus or from the internal

GND

storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions.

The select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred.

A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four

fundamental bus-management functions that can be performed with the SN74BCT651.

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the

appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and

SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when

all the other data sources to the two sets of bus lines are at high impedance, each set will remain at its last state.

The SN74BCT651 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

CLKAB

DATA I/O

A1 THRU A8

OPERATION OR FUNCTION

OEAB

OEBA

CLKBA

SAB

SBA

B1 THRU B8

Input

H or L

Input

Isolation

↑

Input

Store A and B data

†

↑

H or L

Input

Unspecified

Store A, hold B

‡

↑

Input

Output

Input

Store A in both registers

Hold A, store B

†

H or L

↑

Unspecified

Output

Input

‡

↑

Input

Store B in both registers

Real-time B data to A bus

Stored B data to A bus

Real-time A data to B bus

Stored A data to B bus

Input

H or L

Input

Output

H or L

Input

Stored A data to B bus and

stored B data to A bus

H or L

Output

†

‡

The data output functions may be enabled or disabled by various signals at the OEAB or OEBA inputs. Data input functions are always enabled,

i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

When select control is low, clocks can occur simultaneously so long as allowances are made for propagation delays from A to B (B to A) plus

setup and hold times. When select control is high, clocks must be staggered in order to load both registers.

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2−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...10

中文翻译

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与SN74BCT651相关器件

型号	品牌	获取价格	描述	数据表
SN74BCT651DW	TI	获取价格	OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74BCT651DWR	TI	获取价格	OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74BCT651NT	TI	获取价格	OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74BCT652	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DW	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DWE4	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DWG4	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DWR	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DWRE4	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
SN74BCT652DWRG4	TI	获取价格	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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