ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢇ ꢉ ꢄꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢆꢇ ꢈꢉ ꢇꢉ ꢄ
ꢍ ꢎ ꢏꢄꢐ ꢆꢋ ꢄꢑꢒ ꢒꢓ ꢔꢀꢕ ꢖ ꢔꢐ ꢗꢓ ꢔ ꢀ
ꢘ ꢐꢆ ꢙꢋ ꢚ ꢏꢀꢆꢛꢆ ꢓꢋ ꢜꢑ ꢆꢝ ꢑꢆ ꢀ
ꢋ
SCBS080B − DECEMBER 1990 − REVISED NOVEMBER 1993
SN54BCT29828B . . . JT OR W PACKAGE
SN74BCT29828B . . . DW OR NT PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
1
24
23
22
21
20
19
18
17
16
15
14
13
OE1
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
3
• 3-State Inverting Outputs Drive Bus Lines or
4
Buffer Memory Address Registers
5
6
• P-N-P Inputs Reduce dc Loading
7
• Flow-Through Architecture Optimizes
8
PCB Layout
9
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic Chip
Carriers (FK) and Flatpacks (W), and
Standard Plastic and Ceramic 300-mil DIPs
(JT, NT)
10
11
12
A9
A10
GND
SN54BCT29828B . . . FK PACKAGE
(TOP VIEW)
description
These 10-bit buffers and bus drivers provide
high-performance bus interface for wide data
paths or buses carrying parity.
4
3
2
1
28 27 26
25
5
6
7
8
9
Y3
Y4
Y5
A3
A4
A5
NC
A6
A7
A8
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all ten outputs are in
the high-impedance state. The outputs are also in
the high-impedance state during power-up and
power-down conditions. The outputs remain in the
high-impedance state while the device is powered
down.
24
23
22 NC
21 Y6
20 Y7
19 Y8
10
11
12 13 14 15 16 17 18
The SN54BCT29828B is characterized for
operation over the full military temperature range
of −55°C to 125°C. The SN74BCT29828B is
characterized for operation from 0°C to 70°C.
NC − No internal connection
FUNCTION TABLE
INPUTS
OUTPUT
Y
H
L
OE1
L
OE2
L
A
L
L
L
H
X
X
H
X
Z
Z
X
H
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ꢞ
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ꢟ
ꢟ
ꢞ
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ꢦ
ꢪ
ꢧ
ꢨ
ꢢ
ꢢ
ꢩ
ꢩ
ꢟ
ꢥ
ꢤ
ꢣ
ꢦ
ꢦ
ꢡ
ꢠ
ꢪ
ꢆꢩ
ꢨ
ꢫ
ꢦ
ꢬ
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ꢧ
ꢤ
ꢦ
ꢥ
ꢞ
ꢥ
ꢡ
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ꢟ
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ꢮ
Copyright 1993, Texas Instruments Incorporated
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ꢥ ꢩ ꢦ ꢥꢞ ꢟꢳ ꢡꢠ ꢤ ꢬꢬ ꢪꢤ ꢢ ꢤ ꢣ ꢩ ꢥ ꢩ ꢢ ꢦ ꢮ
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1
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