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SN74BCT29823DW-00 PDF预览

SN74BCT29823DW-00

更新时间: 2024-11-14 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 199K
描述
BCT/FBT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24

SN74BCT29823DW-00 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.65Is Samacsys:N
其他特性:WITH CLEAR AND CLOCK ENABLE系列:BCT/FBT
JESD-30 代码:R-PDSO-G24长度:15.4 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:9功能数量:1
端口数量:2端子数量:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
最大电源电流(ICC):35 mA传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:7.5 mm
Base Number Matches:1

SN74BCT29823DW-00 数据手册

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ꢈ ꢋꢄꢌ ꢆꢍ ꢄꢎꢀ ꢋꢌꢁꢆ ꢏꢐ ꢑꢒꢅꢏ ꢍꢑꢓ ꢌ ꢔꢋ ꢑꢓꢕ  
SCBS018D − NOVEMBER 1988 − REVISED NOVEMBER 1993  
DW OR NT PACKAGE  
(TOP VIEW)  
State-of-the-Art BiCMOS Design  
Significantly Reduces I  
CCZ  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 CLKEN  
13 CLK  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic 300-mil DIPs (NT)  
9D 10  
CLR 11  
GND 12  
description  
This 9-bit bus-interface flip-flop features 3-state  
outputs designed specifically for driving highly  
capacitive or relatively low-impedance loads. It is  
particularly suitable for implementing wider buffer  
registers, I/O ports, bidirectional bus drivers with  
parity, and working registers.  
The nine flip-flops are edge-triggered D-type flip-flops. With the clock-enable (CLKEN) input low, the flip-flops  
store data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching  
the outputs. The SN74BCT29823 has noninverting data (D) inputs. Taking the clear (CLR) input low causes the  
nine Q outputs to go low independent of the clock.  
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high  
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need  
for interface or pullup components.  
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN74BCT29823 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLR CLKEN CLK  
D
X
H
L
L
H
H
H
X
X
L
X
X
X
L
H
L
L
L
L
L
H
X
X
X
Q
0
H
Z
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ꢔꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢆꢤꢫ ꢟꢡ ꢌꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ  
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢔꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
Copyright 1993, Texas Instruments Incorporated  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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