ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉꢊ
ꢋ ꢅꢆꢌꢍꢎꢄ ꢏꢀꢎ ꢆꢐꢌ ꢁꢀꢅꢑ ꢒꢓꢑ ꢐꢎꢌꢁꢔ ꢎꢐꢑ ꢕ ꢒꢀ ꢆꢑ ꢐ
ꢖ ꢒꢆ ꢗꢎ ꢊ ꢘꢀꢆꢌꢆ ꢑꢎ ꢋꢏ ꢆꢙ ꢏꢆ ꢀ
SCBS105B − DECEMBER 1990 − REVISED NOVEMBER 1993
DW OR NT PACKAGE
(TOP VIEW)
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V
B8
B7
V
CC
A8
1
24
23
Per MIL-STD-883C, Method 3015
2
• Two 8-Bit, Back-to-Back Registers Store
B6
B5
B4
B3
B2
B1
3
22 A7
21 A6
20 A5
Data Flowing in Both Directions
4
5
• A Port Sinks 24 mA and Sources 3 mA
• B Port Sinks 64 mA and Sources 15 mA
• Inverting Outputs
6
19
18
17
16
15
14
13
A4
A3
A2
A1
OEBA
CLKBA
CLKENBA
7
8
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
9
OEAB
CLKAB
CLKENAB
GND
10
11
12
description
The SN74BCT2953 octal bus transceiver contains two 8-bit back-to-back registers that store data flowing in
both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or
CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low allows access of the data on the
output port (B port or A port).
The SN74BCT2953 is characterized for operation from 0°C to 70°C.
§
†
logic symbol
FUNCTION TABLE
INPUTS
OUTPUT
B
15
OEBA
EN3
G1
CLKENAB CLKAB OEAB
A
X
X
L
13
‡
CLKENBA
H
X
L
X
L
L
L
L
H
B
0
B
0
14
‡
CLKBA
1 C5
H or L
9
↑
↑
X
H
L
EN4
G2
OEAB
11
L
H
X
CLKENAB
10
X
Z
CLKAB
2 C6
†
‡
A-to-B data flow is shown; B-to-A data flow is similar but
uses CLKENBA, CLKBA, and OEBA.
Level of B before the indicated steady-state input
conditions were established.
8
16
5D
4
B1
3
1
1
A1
6D
17
7
6
5
4
3
2
1
A2
B2
B3
B4
B5
B6
B7
B8
18
A3
19
A4
20
A5
21
A6
22
A7
23
A8
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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Copyright 1993, Texas Instruments Incorporated
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2−1
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