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SCES598C – JULY 2004 – REVISED OCTOBER 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Control Inputs V /V Levels Are
IH IL
CCA
1
2
3
6
5
4
V
GND
V
CCB
DIR
CCA
Referenced to V
Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
A
B
YEP OR YZP PACKAGE
(BOTTOM VIEW)
D
D
D
I/Os Are 4.6-V Tolerant
I
Supports Partial-Power-Down Mode
off
3 4
2 5
1 6
A
GND
B
DIR
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CCB
CCA
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track V . V accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
CCA CCA
V
. V
accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
CCB CCB
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCH1T45 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input.
The SN74AVCH1T45 is designed so that the DIR input is powered by V
.
CCA
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74AVCH1T45YEPR
SN74AVCH1T45YZPR
Tape and reel
_ _ _TF_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
SOT (SOT-23) − DBV
Tape and reel SN74AVCH1T45DBVR
Tape and reel SN74AVCH1T45DCKR
ET1_
TF_
SOT (SC-70) − DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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