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SN74AVC1T45DRLR PDF预览

SN74AVC1T45DRLR

更新时间： 2024-11-22 22:48:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
22页 465K
描述
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

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中文翻译

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SN74AVC1T45DRLR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOT
包装说明：VSOF, FL6,.047,20针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.23
Samacsys Confidence：4Samacsys Status：Released
Samacsys PartID：563826Samacsys Pin Count：6
Samacsys Part Category：Integrated CircuitSamacsys Package Category：SO Transistor Flat Lead
Samacsys Footprint Name：DRL (R-PDSO-N6)_1Samacsys Released Date：2017-08-24 14:51:01
Is Samacsys：N其他特性：TWO SEPARATE CONFIGURABLE POWER SUPPLY RAILS FOR PORT A AND PORT B
控制类型：COMMON CONTROL计数方向：BIDIRECTIONAL
系列：AVCJESD-30 代码：R-PDSO-F6
JESD-609代码：e4长度：1.6 mm
负载电容（CL）：15 pF逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：1功能数量：1
端口数量：2端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSOF
封装等效代码：FL6,.047,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：1.5/3.3 V
最大电源电流（ICC）：0.02 mAProp。Delay @ Nom-Sup：5.6 ns
传播延迟（tpd）：5.6 ns认证状态：Not Qualified
座面最大高度：0.6 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：FLAT
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：1.5/3.3V &1.5/3.3V
宽度：1.2 mmBase Number Matches：1

SN74AVC1T45DRLR 数据手册

 浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第2页浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第3页浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第4页浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第5页浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第6页浏览型号SN74AVC1T45DRLR的Datasheet PDF文件第7页 
SN74AVC1T45  
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER  
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS  
www.ti.com  
SCES530D–DECEMBER 2003–REVISED NOVEMBER 2005  
FEATURES  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
Fully Configurable Dual-Rail Design Allows  
Each Port to Operate Over the Full 1.2-V to  
3.6-V Power-Supply Range  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
VCC Isolation Feature - If Either VCC Input Is at  
GND, Both Ports Are in the High-Impedance  
State  
– 1000-V Charged-Device Model (C101)  
•
•
•
DIR Input Circuit Referenced to VCCA  
±12-mA Output Drive at 3.3 V  
I/Os Are 4.6-V Tolerant  
DBV PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
C2  
C1  
3 4  
2 5  
1 6  
A
GND  
B
DIR  
1
2
3
6
5
4
V
V
V
V
CCB  
1
2
3
6
5
4
CCA  
CCB  
CCA  
1
2
3
6
V
V
CCB  
B1  
A1  
B2  
A2  
CCA  
GND  
A
DIR  
B
GND  
A
DIR  
B
V
V
CCB  
CCA  
DIR  
B
GND  
A
5
4
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The  
SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as  
low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The  
B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal  
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74AVC1T45YEPR  
Tape and reel  
_ _ _TC_  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74AVC1T45YZPR  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
SOT (SOT-553) – DRL  
Tape and reel  
Tape and reel  
Reel of 4000  
SN74AVC1T45DBVR  
SN74AVC1T45DCKR  
SN74AVC1T45DRLR  
DT1_  
TC_  
UE_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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SN74AVC1T45DRLR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AVCH1T45DCKR TI

完全替代

 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER
SN74AVCH1T45DBVR TI

完全替代

 SINGLE BIT DUAL SUPPLY BUS TRANSCEIVER
SN74AVC1T45DCKR TI

完全替代

 SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE O

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