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SN74AVC1T45DBVRG4 PDF预览

SN74AVC1T45DBVRG4

更新时间: 2024-11-04 03:23:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
24页 613K
描述
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN74AVC1T45DBVRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOT-23
包装说明:SOT-23, 6 PIN针数:6
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.09
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:738157Samacsys Pin Count:6
Samacsys Part Category:Integrated CircuitSamacsys Package Category:SOT23 (6-Pin)
Samacsys Footprint Name:DBV0006ASamacsys Released Date:2020-05-01 12:53:13
Is Samacsys:N其他特性:TWO SEPARATE CONFIGURABLE POWER SUPPLY RAILS FOR PORT A AND PORT B
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:AVCJESD-30 代码:R-PDSO-G6
JESD-609代码:e4长度:2.9 mm
负载电容(CL):15 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.012 A湿度敏感等级:1
位数:1功能数量:1
端口数量:2端子数量:6
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:1.5/3.3 V
最大电源电流(ICC):0.02 mAProp。Delay @ Nom-Sup:5.6 ns
传播延迟(tpd):5.6 ns认证状态:Not Qualified
座面最大高度:1.45 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:1.5/3.3V &1.5/3.3V
宽度:1.6 mmBase Number Matches:1

SN74AVC1T45DBVRG4 数据手册

 浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第2页浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第3页浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第4页浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第5页浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第6页浏览型号SN74AVC1T45DBVRG4的Datasheet PDF文件第7页 
SN74AVC1T45  
SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER  
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS  
www.ti.com  
SCES530GDECEMBER 2003REVISED JANUARY 2008  
1
FEATURES  
2
Available in the Texas Instruments NanoFree™  
Package  
Typical Max Data Rates  
500 Mbps (1.8-V to 3.3-V Translation)  
320 Mbps (<1.8-V to 3.3-V Translation)  
320 Mbps (Translate to 2.5 V or 1.8 V)  
280 Mbps (Translate to 1.5 V)  
Fully Configurable Dual-Rail Design Allows  
Each Port to Operate Over the Full 1.2-V to  
3.6-V Power-Supply Range  
VCC Isolation Feature - If Either VCC Input Is at  
GND, Both Ports Are in the High-Impedance  
State  
240 Mbps (Translate to 1.2 V)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
DIR Input Circuit Referenced to VCCA  
±12-mA Output Drive at 3.3 V  
I/Os Are 4.6-V Tolerant  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Ioff Supports Partial-Power-Down Mode  
Operation  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
C2  
C1  
3 4  
2 5  
1 6  
A
GND  
VCCA  
B
DIR  
VCCB  
1
2
3
6
5
4
VCCA  
GND  
A
VCCB VCCA  
VCCB  
DIR  
B
1
2
3
6
5
4
1
2
3
6
VCCA  
GND  
A
VCCB  
DIR  
B
B1  
A1  
B2  
A2  
GND  
DIR  
A
5
4
B
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The  
SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as  
low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The  
B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal  
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(3)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SOT (SOT-23) – DBV  
Reel of 3000  
SN74AVC1T45YZPR  
_ _ _TC_  
Reel of 3000  
Reel of 3000  
Reel of 4000  
SN74AVC1T45DBVR  
SN74AVC1T45DCKR  
SN74AVC1T45DRLR  
DT1_  
TC_  
TC_  
–40°C to 85°C  
SOT (SC-70) – DCK  
SOT (SOT-553) – DRL  
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2008, Texas Instruments Incorporated  

SN74AVC1T45DBVRG4 替代型号

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SN74AVC1T45DBVT TI

完全替代

SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE O
SN74AVC1T45DBVR TI

完全替代

SINGLE-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE O

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