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SN74AUP2G126YZPR PDF预览

SN74AUP2G126YZPR

更新时间： 2024-11-16 05:17:39
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
16页 514K
描述
LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74AUP2G126YZPR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：DSBGA-8针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.33Is Samacsys：N
控制类型：ENABLE HIGH计数方向：UNIDIRECTIONAL
系列：AUP/ULP/VJESD-30 代码：R-PBGA-B8
JESD-609代码：e1长度：1.9 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.004 A湿度敏感等级：1
位数：2功能数量：1
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
最大电源电流（ICC）：0.0009 mAProp。Delay @ Nom-Sup：31.2 ns
传播延迟（tpd）：18.7 ns认证状态：Not Qualified
座面最大高度：0.5 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.1 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：0.9 mmBase Number Matches：1

SN74AUP2G126YZPR 数据手册

 浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第2页浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第3页浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第4页浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第5页浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第6页浏览型号SN74AUP2G126YZPR的Datasheet PDF文件第7页 
SN74AUP2G126  
LOW-POWER DUAL BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES687B–JANUARY 2007–REVISED JANUARY 2008  
1
FEATURES  
2
•
Available in the Texas Instruments NanoFree™  
Package  
and Better Switching Noise Immunity at Input  
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
•
•
•
•
•
Low Static-Power Consumption  
(ICC = 0.9 µA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4 pF Typ at 3.3 V)  
•
•
•
tpd = 4.6 ns Max at 3.3 V  
•
•
Low Input Capacitance (Ci = 1.5 pF Typ)  
Suitable for Point-to-Point Applications  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
•
•
Input-Disable Feature Allows Floating Input  
Conditions  
•
ESD Performance Tested Per JESD 22  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
200-V Machine Model (A115-A)  
Input Hysteresis Allows Slow Input Transition  
1000-V Charged-Device Model (C101)  
DCU PACKAGE  
(TOP VIEW)  
RSE PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
YFP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
4 5  
GND  
2Y  
2A  
1Y  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
3 6  
2 7  
1 8  
1Y  
3 6  
2 7  
1 8  
1A  
2OE  
VCC  
1A  
2OE  
VCC  
1OE  
1
2
3
8
4
2OE  
7
6
5
1OE  
1A  
2Y  
1OE  
GND  
2A  
1Y  
2A  
2Y  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
Switching Characteristics  
at 25 MHz†  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
(mA)  
3.5  
3
100%  
80%  
100%  
80%  
2.5  
Input  
Output  
2
1.5  
1
60%  
40%  
60%  
40%  
3.3-V  
Logic†  
3.3-V  
Logic†  
0.5  
0
20%  
0%  
20%  
0%  
AUP  
AUP  
-0.5  
10  
15  
20  
25  
Time - ns  
0
5
35  
40  
45  
30  
†
Single, dual, and triple gates  
†
AUP1G08 data at CL = 15 pF  
Figure 1. AUP – The Lowest Power Family  
Figure 2. Excellent Signal Integrity  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2007–2008, Texas Instruments Incorporated  
 
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SN74AUP2G126YZPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUP2G126DCUR TI

完全替代

 具有三态输出的 2 通道、0.8V 至 3.6V 低功耗缓冲器 | DCU | 8 | -
SN74AUP2G126RSER TI

完全替代

 Low-Power Dual Bus Buffer Gate With 3-State Outputs 8-UQFN -40 to 85
SN74AUP2G126YFPR TI

完全替代

 LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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