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SN74AUP1G34

更新时间： 2024-11-01 23:03:11
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
13页 289K
描述
LOW-POWER SINLE BUFFER GATE

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SN74AUP1G34 数据手册

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SCES603B – AUGUST 2004 – REVISED JUNE 2005  
D
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Low Static-Power Consumption;  
D
D
D
D
D
D
Wide Operating V  
Range of 0.8 V to 3.6 V  
CC  
Optimized for 3.3-V Operation  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
I
= 0.9 µA Max  
CC  
Low Dynamic-Power Consumption;  
= 4.1 pF Typ at 3.3 V  
t
= 3.8 ns Max at 3.3 V  
pd  
C
pd  
Suitable for Point-to-Point Applications  
D
Low Input Capacitance; C = 1.5 pF Typ  
i
Low Noise − Overshoot and Undershoot  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
<10% of V  
CC  
D
ESD Performance Tested Per JESD 22  
− 2000-V Human-Body Model  
(A114-B, Class II)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Input Hysteresis Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
D
ESD Protection Exceeds 5000 V With  
Human-Body Model  
(V  
= 250 mV Typ at 3.3 V)  
hys  
DCK PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
DBV PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
Y
3
2
1
4
5
GND  
NC  
A
V
Y
1
2
3
5
1
2
3
5
NC  
A
V
Y
CC  
CC  
1
2
3
5
4
NC  
A
V
Y
CC  
A
V
DNU  
CC  
4
GND  
4
GND  
DNU – Do not use  
GND  
See mechanical drawings for dimensions.  
description/ordering information  
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire V range  
CC  
of 0.8 V to 3.6 V resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figures 1 and 2).  
Switching Characteristics  
†
at 25 MHz  
Static-Power Consumption  
Dynamic-Power Consumption  
(pF)  
100%  
3.5  
3
(µA)  
100%  
2.5  
2
80%  
60%  
80%  
Input  
Output  
1.5  
1
60%  
40%  
3.3-V  
3.3-V  
†  
Logic  
†
Logic  
40%  
0.5  
0
20%  
0%  
20%  
0%  
−0.5  
10  
15 20  
Time − ns  
AUP1G08 data at C = 15 pF  
0
5
25  
35 40 45  
AUP  
AUP  
30  
†
†
Single, dual, and triple gates  
L
Figure 1. AUP − The Lowest-Power Family  
Figure 2. Excellent Signal Integrity  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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