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SN74AUP1G07DRLRG4 PDF预览

SN74AUP1G07DRLRG4

更新时间: 2024-11-02 09:15:19
品牌 Logo 应用领域
德州仪器 - TI 驱动器栅极触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
21页 975K
描述
LOW-POWER SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS

SN74AUP1G07DRLRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOT
包装说明:VSSOP, FL6,.047,20针数:5
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.44系列:AUP/ULP/V
JESD-30 代码:R-PDSO-G5JESD-609代码:e4
长度:1.6 mm负载电容(CL):30 pF
逻辑集成电路类型:BUFFER最大I(ol):0.0017 A
湿度敏感等级:1功能数量:1
输入次数:1端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:VSSOP封装等效代码:FL6,.047,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:1.2/3.3 VProp。Delay @ Nom-Sup:21.9 ns
传播延迟(tpd):14.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.6 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):0.8 V标称供电电压 (Vsup):1.1 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.2 mmBase Number Matches:1

SN74AUP1G07DRLRG4 数据手册

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SN74AUP1G07  
www.ti.com  
SCES591F JULY 2004REVISED MAY 2010  
LOW-POWER SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS  
Check for Samples: SN74AUP1G07  
1
FEATURES  
Available in the Texas Instruments NanoStar™  
Package  
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Maximum)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 1 pF Typical at 3.3 V)  
tpd = 3.3 ns Maximum at 3.3 V  
Suitable for Point-to-Point Applications  
Low Input Capacitance (Ci = 1.5 pF Typical)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
ESD Performance Tested Per JESD 22  
Ioff Supports Partial-Power-Down Mode  
Operation  
2000-V Human-Body Model  
(A114-B, Class II)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at the  
Input (Vhys = 250 mV Typ at 3.3 V)  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
N.C.  
VCC  
N.C.  
A
VCC  
1
2
5
1
5
N.C.  
A
VCC  
A
4
GND  
Y
2
3
3
4
GND  
Y
4
Y
GND  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
A2  
A2  
N.C.  
A
A1  
1
2
4
3
A1  
B1  
1
2
5
VCC  
N.C.  
Y
A
VCC  
Y
DNU  
A
VCC  
Y
1
2
3
6
5
4
N.C.  
VCC  
N.C.  
Y
GND B1  
B2  
A
C1 3  
4
C2  
GND  
GND  
GND  
N.C. – No internal connection.  
DNU – Do not use  
See mechancial drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 

SN74AUP1G07DRLRG4 替代型号

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