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SN74AUP1G04DSFR PDF预览

SN74AUP1G04DSFR

更新时间: 2024-11-24 11:47:31
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
21页 940K
描述
LOW-POWER SINGLE INVERTER GATE

SN74AUP1G04DSFR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SON
包装说明:VSON, SOLCC6,.04,14针数:6
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.58Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:606847
Samacsys Pin Count:6Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SON35P100X100X40-6N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
系列:AUP/ULP/VJESD-30 代码:S-PDSO-N6
JESD-609代码:e4长度:1 mm
负载电容(CL):30 pF逻辑集成电路类型:INVERTER
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1输入次数:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装等效代码:SOLCC6,.04,14
封装形状:SQUARE封装形式:SMALL OUTLINE, VERY THIN PROFILE
包装方法:TR峰值回流温度(摄氏度):260
电源:1.2/3.3 V最大电源电流(ICC):0.0009 mA
Prop。Delay @ Nom-Sup:19 ns传播延迟(tpd):19 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.4 mm子类别:Gates
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.1 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.35 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1 mm
Base Number Matches:1

SN74AUP1G04DSFR 数据手册

 浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第2页浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第3页浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第4页浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第5页浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第6页浏览型号SN74AUP1G04DSFR的Datasheet PDF文件第7页 
SN74AUP1G04  
www.ti.com  
SCES571H JUNE 2004REVISED MARCH 2010  
LOW-POWER SINGLE INVERTER GATE  
Check for Samples: SN74AUP1G04  
1
FEATURES  
Available in the Texas Instruments NanoStar™  
Package  
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4.1 pF Typ at 3.3 V)  
tpd = 3.9 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
Low Input Capacitance (Ci = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise Overshoot and Undershoot  
<10% of VCC  
ESD Performance Tested Per JESD 22  
Ioff Supports Partial-Power-Down Mode  
Operation  
2000-V Human-Body Model  
(A114-B, Class II)  
Input Hysteresis Allows Slow Input Transition  
and Better Switching Noise Immunity at the  
Input (Vhys = 250 mV Typ at 3.3 V)  
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
N.C.  
A
VCC  
N.C.  
A
VCC  
1
2
5
1
5
N.C.  
A
VCC  
4
GND  
Y
2
3
3
4
GND  
Y
4
Y
GND  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
A2  
N.C.  
A
A1  
1
2
4
3
VCC  
N.C.  
Y
A
VCC  
Y
1
2
3
6
5
4
N.C.  
A
VCC  
N.C.  
Y
GND B1  
B2  
GND  
GND  
N.C. – No internal connection.  
DNU – Do not use  
See mechancial drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low power needs in battery-powered portable  
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see  
Figure 1 and Figure 2).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 

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