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SN74AUC1G32DRLRG4 PDF预览

SN74AUC1G32DRLRG4

更新时间: 2024-11-24 11:50:55
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
14页 659K
描述
SINGLE 2-INPUT POSITIVE-OR GATE

SN74AUC1G32DRLRG4 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP-5
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.49
Is Samacsys:N系列:AUC
JESD-30 代码:R-PDSO-F5JESD-609代码:e4
长度:1.6 mm负载电容(CL):15 pF
逻辑集成电路类型:OR GATE最大I(ol):0.005 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSOF
封装等效代码:FL6,.047,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:1.2/2.5 V
Prop。Delay @ Nom-Sup:3.5 ns传播延迟(tpd):3.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:0.6 mm子类别:Gates
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):0.8 V
标称供电电压 (Vsup):1.2 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:FLAT
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.2 mm
Base Number Matches:1

SN74AUC1G32DRLRG4 数据手册

 浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第2页浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第3页浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第4页浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第5页浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第6页浏览型号SN74AUC1G32DRLRG4的Datasheet PDF文件第7页 
SN74AUC1G32  
www.ti.com ................................................................................................................................... SCES377OSEPTEMBER 2001REVISED SEPTEMBER 2009  
SINGLE 2-INPUT POSITIVE-OR GATE  
1
FEATURES  
2
Available in the Texas Instruments NanoFree™  
Package  
Max tpd of 2.4 ns at 1.8 V  
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Ioff Supports Partial-Power-Down Mode  
Operation  
ESD Protection Exceeds JESD 22  
2000-V Human-Body Model (A114-A)  
1000-V Charged-Device Model (C101)  
Sub-1-V Operable  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
5
4
A
B
VCC  
1
2
3
5
A
VCC  
1
2
3
5
VCC  
A
B
B
GND  
Y
4
GND  
Y
4
GND  
Y
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
C1  
B1  
A1  
C2  
3
2
1
4
GND  
B
Y
1
2
3
6
5
4
A
B
VCC  
NC  
A2  
5
A
VCC  
Y
GND  
NC - No internal connections  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to  
1.95-V VCC operation.  
Y + A ) B or Y + A · B  
The SN74AUC1G32 performs the Boolean function  
in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of  
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2009, Texas Instruments Incorporated  

SN74AUC1G32DRLRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G32DRLR TI

完全替代

SINGLE 2-INPUT POSITIVE-OR GATE
NL17SV32XV5T2G ONSEMI

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NL17SV32XV5T2 ONSEMI

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