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SN74AUC1G125_08

更新时间： 2024-11-02 11:48:51
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德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 462K
描述
SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT

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SN74AUC1G125_08 数据手册

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SN74AUC1G125  
SINGLE BUS BUFFER GATE  
WITH 3-STATE OUTPUT  
www.ti.com  
SCES382K–MARCH 2002–REVISED APRIL 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10-µA Max ICC  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 2.5 ns at 1.8 V  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
Y
VCC  
GND  
A
OE  
A
1
2
3
6
5
4
1
2
3
5
OE  
A
VCC  
NC  
Y
1
2
3
5
OE  
A
VCC  
5
VCC  
OE  
GND  
4
GND  
Y
4
Y
GND  
NC – No internal connection  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC  
operation.  
The SN74AUC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable  
(OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SON – DRY  
Reel of 3000  
SN74AUC1G125YZPR  
_ _ _UM_  
Reel of 5000  
Reel of 3000  
Reel of 3000  
SN74AUC1G125DRYR  
SN74AUC1G125DBVR  
SN74AUC1G125DCKR  
PREVIEW  
U25_  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
UM_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(3) DBV/DCK/DRY: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
UNLESS OTHERWISE NOTED this document contains  
Copyright © 2002–2007, Texas Instruments Incorporated  
PRODUCTION DATA information current as of publication date.  
Products conform to specifications per the terms of Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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