ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢉ ꢊ
ꢀꢋ ꢁꢈ ꢌ ꢍ ꢊ ꢎꢋꢁ ꢏꢅꢐ ꢏꢑ ꢀꢋ ꢐ ꢋꢒꢍ ꢎꢁꢑ ꢓ ꢈ ꢄꢐꢍ
SCES369M − SEPTEMBER 2001 − REVISED MAY 2005
D
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D
D
D
D
Low Power Consumption, 10-µA Max I
8-mA Output Drive at 1.8 V
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
I
Supports Partial-Power-Down Mode
off
Operation
D
Sub 1-V Operable
− 1000-V Charged-Device Model (C101)
D
Max t of 2.4 ns at 1.8 V
pd
DCK PACKAGE
(TOP VIEW)
YEA, YEP, YZA,
DRL PACKAGE
DBV PACKAGE
(TOP VIEW)
OR YZP PACKAGE
(TOP VIEW)
(BOTTOM VIEW)
1
2
3
5
4
A
B
V
1
2
3
5
A
B
V
Y
CC
3
2
1
4
CC
Y
GND
B
1
2
3
5
4
A
B
V
Y
CC
5
GND
V
A
CC
4
GND
Y
GND
See mechanical drawings for dimensions.
description/ordering information
This single 2-input positive-NOR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V
CC
to 1.95-V V
operation.
CC
The SN74AUC1G02 performs the Boolean function Y = A + B or Y = A • B in positive logic.
ORDERING INFORMATION
†
‡
T
A
PACKAGE
ORDERABLE PART NUMBER
TOP-SIDE MARKING
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74AUC1G02YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
SN74AUC1G02YZAR
SN74AUC1G02YEPR
SN74AUC1G02YZPR
Tape and reel
_ _ _UB_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
Tape and reel
Tape and reel
SN74AUC1G02DBVR
SN74AUC1G02DCKR
U02_
UB_
SOT (SOT-553) − DRL
Reel of 4000
SN74AUC1G02DRLR
UB_
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
ꢏ
ꢏ
ꢓ
ꢑ
ꢤ
ꢔ
ꢟ
ꢅ
ꢆ
ꢝ
ꢐ
ꢞ
ꢋ
ꢘ
ꢑ
ꢖ
ꢁ
ꢗ
ꢔ
ꢄ
ꢐ
ꢄ
ꢕ
ꢖ
ꢠ
ꢗ
ꢘ
ꢞ
ꢙ
ꢚ
ꢛ
ꢛ
ꢜ
ꢜ
ꢕ
ꢕ
ꢘ
ꢘ
ꢖ
ꢖ
ꢕ
ꢝ
ꢝ
ꢡ
ꢞ
ꢟ
ꢙ
ꢙ
ꢠ
ꢠ
ꢖ
ꢜ
ꢛ
ꢚ
ꢝ
ꢝ
ꢘ
ꢗ
ꢡ
ꢐꢠ
ꢟ
ꢢ
ꢝ
ꢣ
ꢕ
ꢞ
ꢛ
ꢝ
ꢜ
ꢕ
ꢜ
ꢘ
ꢙ
ꢖ
ꢟ
ꢤ
ꢛ
ꢖ
ꢜ
ꢜ
ꢠ
ꢝ
ꢥ
Copyright 2005, Texas Instruments Incorporated
ꢙ
ꢘ
ꢞ
ꢜ
ꢘ
ꢙ
ꢚ
ꢜ
ꢘ
ꢝ
ꢡ
ꢕ
ꢗ
ꢕ
ꢞ
ꢠ
ꢙ
ꢜ
ꢦ
ꢜ
ꢠ
ꢙ
ꢘ
ꢗ
ꢧ
ꢛ
ꢋ
ꢖ
ꢚ
ꢠ
ꢝ
ꢜ
ꢛ
ꢖ
ꢤ
ꢛ
ꢙ
ꢤ
ꢨ
ꢛ
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ
ꢙ
ꢙ
ꢛ
ꢖ
ꢜ
ꢩ
ꢥ
ꢏ
ꢙ
ꢘ
ꢤ
ꢟ
ꢞ
ꢜ
ꢕ
ꢘ
ꢖ
ꢡ
ꢙ
ꢘ
ꢞ
ꢠ
ꢝ
ꢝ
ꢕ
ꢖ
ꢪ
ꢤ
ꢘ
ꢠ
ꢝ
ꢖ
ꢘ
ꢜ
ꢖ
ꢠ
ꢞ
ꢠ
ꢝ
ꢝ
ꢛ
ꢙ
ꢕ
ꢣ
ꢩ
ꢕ
ꢖ
ꢞ
ꢣ
ꢟ
ꢤ
ꢠ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265