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SN74AUC1G00YEPR

更新时间： 2024-11-19 22:08:39
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路输入元件
页数 文件大小 规格书
12页 309K
描述
SINGLE 2 INPUT POSITIVE NAND GATE

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中文翻译

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SN74AUC1G00YEPR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA, BGA5,2X3,20
针数：5Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.6系列：AUC
JESD-30 代码：R-XBGA-B5长度：1.4 mm
逻辑集成电路类型：NAND GATE最大I（ol）：0.005 A
功能数量：1输入次数：2
端子数量：5最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：UNSPECIFIED封装代码：VFBGA
封装等效代码：BGA5,2X3,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.2/2.5 V
传播延迟（tpd）：3.2 ns认证状态：Not Qualified
施密特触发器：NO座面最大高度：0.5 mm
子类别：Gates最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
Base Number Matches：1

SN74AUC1G00YEPR 数据手册

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SCES368K − SEPTEMBER 2001 − REVISED NOVEMBER 2003  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
2
3
5
4
A
B
GND  
V
Y
CC  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
D
D
D
D
D
Sub 1-V Operable  
Max t of 2.2 ns at 1.8 V  
pd  
Low Power Consumption, 10-µA Max I  
3 4  
2
GND  
B
Y
V
CC  
8-mA Output Drive at 1.8 V  
1 5  
A
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This single 2-input positive-NAND gate is operational at 0.8-V to 2.7-V V , but is designed specifically for  
CC  
1.65-V to 1.95-V V  
operation.  
CC  
The SN74AUC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.17-mm Small Bump − YEA  
SN74AUC1G00YEAR  
NanoFree− WCSP (DSBGA)  
0.17-mm Small Bump − YZA (Pb-free)  
SN74AUC1G00YZAR  
SN74AUC1G00YEPR  
SN74AUC1G00YZPR  
Tape and reel  
_ _ _UA_  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
−40°C to 85°C  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SOT (SOT-23) − DBV  
SOT (SC-70) − DCK  
Tape and reel  
Tape and reel  
SN74AUC1G00DBVR  
SN74AUC1G00DCKR  
U00_  
UA_  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,  
and one following character to designate the assembly/test site.Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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SN74AUC1G00YEPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G00YZPR TI

完全替代

 SINGLE 2 INPUT POSITIVE NAND GATE
SN74AUC1G00YZAR TI

完全替代

 SINGLE 2 INPUT POSITIVE NAND GATE
SN74AUC1G00YEAR TI

完全替代

 SINGLE 2 INPUT POSITIVE NAND GATE

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