SN74AS885FN

更新时间： 2024-11-20 13:13:47

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
9页	155K
描述
暂无描述

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN74AS885FN 数据手册

SN54AS885, SN74AS885

8-BIT MAGNITUDE COMPARATORS

SDAS236A – DECEMBER 1982 – REVISED JANUARY 1995

SN54AS885 . . . JT PACKAGE

SN74AS885 . . . DW OR NT PACKAGE

(TOP VIEW)

• Latchable P-Input Ports With Power-Up

Clear

• Choice of Logical or Arithmetic

(Two’s Complement) Comparison

L/A

P < QIN

P > QIN

23 PLE

• Data and PLE Inputs Utilize pnp Input

Transistors to Reduce dc Loading Effects

22 P7

21 P6

• Approximately 35% Improvement in

ac Performance Over Schottky TTL While

Performing More Functions

20 P5

19 P4

18 P3

• Cascadable to n Bits While Maintaining

17 P2

High Performance

16 P1

• 10% Less Power Than STTL for an 8-Bit

Q1 10

Q0 11

15 P0

Comparison

14 P < QOUT

13 P > QOUT

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

GND 12

SN54AS885 . . . FK PACKAGE

(TOP VIEW)

description

These advanced Schottky devices are capable of

performing high-speed arithmetic or logic

comparisons on two 8-bit binary or two’s

complement words. Two fully decoded decisions

about words P and Q are externally available at

two outputs. These devices are fully expandable

to any number of bits without external gates. To

compare words of longer lengths, the P > QOUT

and P < QOUT outputs of a stage handling less

significant bits can be connected to the P > QIN

and P < QIN inputs of the next stage handling

more significant bits. The cascading paths are

implemented with only a two-gate-level delay to

reduce overall comparison times for long words.

Two alternative methods of cascading are shown

in application information.

28 27 26

12 13 14 15 16 17 18

NC – No internal connection

The latch is transparent when P latch-enable

(PLE) input is high; the P-input port is latched

when PLE is low. This provides the designer with temporary storage for the P-data word. The enable circuitry

is implemented with minimal delay times to enhance performance when cascaded for longer words. The PLE,

P, and Q data inputs utilize pnp input transistors to reduce the low-level current input requirement to typically

–0.25 mA, which minimizes dc loading effects.

The SN54AS885 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74AS885 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...9

中文翻译

下载PDF

与SN74AS885FN相关器件

型号	品牌	获取价格	描述	数据表
SN74AS885FN-00	TI	获取价格	AS SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PQCC28
SN74AS885JTP4	TI	获取价格	IC,MAGNITUDE COMPARATOR,AS-TTL,DIP,24PIN,CERAMIC
SN74AS885NT	TI	获取价格	8-BIT MAGNITUDE COMPARATORS
SN74AS885NT-10	TI	获取价格	AS SERIES, 8-BIT MAGNITUDE COMPARATOR, TRUE OUTPUT, PDIP24
SN74AS885NT3	TI	获取价格	8-BIT MAGNITUDE COMPARATORS
SN74AS885NTE4	TI	获取价格	8-BIT MAGNITUDE COMPARATORS
SN74AS885NTP1	TI	获取价格	IC,MAGNITUDE COMPARATOR,AS-TTL,DIP,24PIN,PLASTIC
SN74AS887-1GB	TI	获取价格	8-BIT, BIT-SLICE MICROPROCESSOR, CPGA68, HERMETIC SEALED, CERAMIC, PGA-68
SN74AS888-1GB	ROCHESTER	获取价格	8-BIT, BIT-SLICE MICROPROCESSOR, CPGA68, HERMETIC SEALED, CERAMIC, PGA-68
SN74AS95AD	TI	获取价格	IC,SHIFT REGISTER,AS-TTL,SOP,14PIN,PLASTIC

与SN74AS885FN相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

24
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

16
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

48
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AS885FN

SN74AS885FN 数据手册

与SN74AS885FN相关器件

与SN74AS885FN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AS885FN

SN74AS885FN 数据手册

与SN74AS885FN相关器件

与SN74AS885FN相关文章

您还可以找

您在本页遇到什么问题？