SN74AS825A

更新时间： 2024-09-30 23:03:11

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
7页	108K
描述
8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74AS825A 数据手册

SN54AS825A, SN74AS825A

8-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS020B – JUNE 1984 – REVISED AUGUST 1995

SN54AS825A . . . JT PACKAGE

SN74AS825A . . . DW OR NT PACKAGE

(TOP VIEW)

• Functionally Equivalent to AMD’s AM29825

• Improved I Specifications

• Multiple Output Enables Allow Multiuser

Control of the Interface

OE1

OE2

23 OE3

22 1Q

21 2Q

20 3Q

19 4Q

18 5Q

17 6Q

16 7Q

15 8Q

14 CLKEN

13 CLK

• Outputs Have Undershoot-Protection

Circuitry

• Power-Up High-Impedance State

• Buffered Control Inputs Reduce dc

Loading Effects

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

8D 10

CLR 11

GND 12

description

These 8-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. These devices

are particularly suitable for implementing

multiuser registers, I/O ports, bidirectional bus

drivers, and working registers.

SN54AS825A . . . FK PACKAGE

(TOP VIEW)

28 27 26

With the clock-enable (CLKEN) input low, the

eight D-type edge-triggered flip-flops enter data

on the low-to-high transitions of the clock (CLK)

input. Taking CLKEN high disables the clock

buffer, latching the outputs. These devices have

noninverting data (D) inputs. Taking the clear

(CLR) input low causes the eight Q outputs to go

low independently of the clock.

12 13 14 15 16 17 18

Multiuser buffered output-enable (OE1, OE2, and

OE3) inputs can be used to place the eight outputs

in either a normal logic state (high or low logic

NC – No internal connection

level) or

a high-impedance state. In the

high-impedance state, the outputs neither load

nor drive the bus lines significantly. The high-

impedance state and increased drive provide the

capability to drive bus lines without interface or

pullup components.

The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data

can be entered while the outputs are in the high-impedance state.

The SN54AS825A is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74AS825A is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN74AS825A相关器件

型号	品牌	获取价格	描述	数据表
SN74AS825ADW	TI	获取价格	8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS825ADWE4	TI	获取价格	IC AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24, Bus Driver/Transceiver
SN74AS825ADWG4	TI	获取价格	AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74AS825ADWR	TI	获取价格	AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24
SN74AS825ADWRE4	TI	获取价格	IC AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24, PLASTIC, SO-24, Bus Driver/Transceiver
SN74AS825ANT	TI	获取价格	8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS825ANTE4	TI	获取价格	AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
SN74AS825DW3	TI	获取价格	IC IC,FLIP-FLOP,OCTAL,D TYPE,AS-TTL,SOP,24PIN,PLASTIC, FF/Latch
SN74AS825DWP3	TI	获取价格	IC IC,FLIP-FLOP,OCTAL,D TYPE,AS-TTL,SOP,24PIN,PLASTIC, FF/Latch
SN74AS825DWR	TI	获取价格	AS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO24

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