SN74AS821A

更新时间： 2024-09-30 23:03:11

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
6页	95K
描述
10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74AS821A 数据手册

SN54AS821A, SN74AS821A

10-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS230A – DECEMBER 1983 – REVISED AUGUST 1995

SN54AS821A . . . JT PACKAGE

SN74AS821A . . . DW OR NT PACKAGE

(TOP VIEW)

• Functionally Equivalent to AMD’s AM29821

• Provide Extra Data Width Necessary for

Wider Address/Data Paths or Buses With

Parity

• Outputs Have Undershoot-Protection

23 1Q

22 2Q

21 3Q

20 4Q

19 5Q

18 6Q

17 7Q

16 8Q

15 9Q

14 10Q

13 CLK

Circuitry

• Power-Up High-Impedance State

• Buffered Control Inputs to Reduce

dc Loading Effects

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Plastic

(NT) and Ceramic (JT) 300-mil DIPs

9D 10

10D 11

GND 12

description

These 10-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing wider buffer

registers, I/O ports, bidirectional bus drivers with

parity, and working registers.

SN54AS821A . . . FK PACKAGE

(TOP VIEW)

28 27 26

The ten flip-flops are edge-triggered D-type

flip-flops. On the positive transition of the clock

(CLK) input, the Q outputs are true to the data (D)

input.

A buffered output-enable (OE) input can be used

to place the ten outputs in either a normal logic

state (high or low logic levels) or a high-

impedance state. In the high-impedance state, the

outputs neither load nor drive the bus lines

significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines without interface or pullup components.

12 13 14 15 16 17 18

NC – No internal connection

OE does not affect the internal operation of the flip-flops. Previously stored data can be retained or new data

can be entered while the outputs are in the high-impedance state.

The SN54AS821A is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74AS821A is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLK

↑

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6

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与SN74AS821A相关器件

型号	品牌	获取价格	描述	数据表
SN74AS821ADW	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS821ADWE4	TI	获取价格	AS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SO-24
SN74AS821ADWG4	TI	获取价格	AS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74AS821ADWR	TI	获取价格	AS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SO-24
SN74AS821ADWRE4	TI	获取价格	AS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SO-24
SN74AS821ANT	TI	获取价格	10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS821DW	TI	获取价格	10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS821FN	TI	获取价格	10-BIT BUS INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS821FN-00	TI	获取价格	AS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PQCC28
SN74AS821JTP4	TI	获取价格	IC IC,FLIP-FLOP,10-BIT,D TYPE,AS-TTL,DIP,24PIN,CERAMIC, FF/Latch

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