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SN74AS573ADW PDF预览

SN74AS573ADW

更新时间: 2024-11-14 22:39:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 134K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74AS573ADW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SO-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.41
Is Samacsys:N其他特性:BROADSIDE VERSION OF 373
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:ASJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.048 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):93 mAProp。Delay @ Nom-Sup:8 ns
传播延迟(tpd):7.5 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

SN74AS573ADW 数据手册

 浏览型号SN74AS573ADW的Datasheet PDF文件第2页浏览型号SN74AS573ADW的Datasheet PDF文件第3页浏览型号SN74AS573ADW的Datasheet PDF文件第4页浏览型号SN74AS573ADW的Datasheet PDF文件第5页浏览型号SN74AS573ADW的Datasheet PDF文件第6页浏览型号SN74AS573ADW的Datasheet PDF文件第7页 
SN54ALS573C, SN54AS573A, SN74ALS573C, SN74AS573A  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SDAS048D – DECEMBER 1989 – REVISED JANUARY 1995  
SN54ALS573C, SN54AS573A . . . J OR W PACKAGE  
SN74ALS573C, SN74AS573A . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
Bus-Structured Pinout  
True Logic Outputs  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Flat  
(W) Packages  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
description  
13 7Q  
12 8Q  
These octal D-type transparent latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
11  
GND  
LE  
SN54ALS573C, SN54AS573A . . . FK PACKAGE  
(TOP VIEW)  
While the latch-enable (LE) input is high, outputs  
(Q) respond to the data (D) inputs. When LE islow,  
the outputs are latched to retain the data that was  
set up.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or a high-impedance state. In  
thehigh-impedancestate, theoutputsneitherload  
nor drive the bus lines significantly. The  
high-impedance state and the increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operation of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range  
of 55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AS573ADW 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS573AN TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74AS573ADWR TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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