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SN74AS374DWR PDF预览

SN74AS374DWR

更新时间： 2024-11-14 05:04:51
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
21页 602K
描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74AS374DWR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.44Is Samacsys：N
系列：ASJESD-30 代码：R-PDSO-G20
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：125000000 Hz
最大I（ol）：0.048 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：128 mA
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

SN74AS374DWR 数据手册

 浏览型号SN74AS374DWR的Datasheet PDF文件第2页浏览型号SN74AS374DWR的Datasheet PDF文件第3页浏览型号SN74AS374DWR的Datasheet PDF文件第4页浏览型号SN74AS374DWR的Datasheet PDF文件第5页浏览型号SN74AS374DWR的Datasheet PDF文件第6页浏览型号SN74AS374DWR的Datasheet PDF文件第7页 
SN54ALS374A, SN54AS374, SN74ALS374A, SN74AS374  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS167C – APRIL 1982 – REVISED NOVEMBER 1999  
SN54ALS374A, SN54AS374 . . . J PACKAGE  
SN74ALS374A, SN74AS374 . . . DW OR N PACKAGE  
(TOP VIEW)  
D-Type Flip-Flops in a Single Package With  
3-State Bus Driving True Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), and Standard Plastic (N)  
and Ceramic (J) DIPs  
description  
13 5D  
12 5Q  
These octal D-type edge-triggered flip-flops  
feature 3-state outputs designed specifically for  
11  
GND  
CLK  
driving  
highly  
capacitive  
or  
relatively  
low-impedance loads. They are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
SN54ALS374A, SN54AS374 . . . FK PACKAGE  
(TOP VIEW)  
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the logic levels set up at  
the data (D) inputs.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and the increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range  
of –55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
↑
↑
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

中文翻译

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SN74AS374DWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AS374NSR TI

完全替代

 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS374DW TI

完全替代

 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS373DW TI

类似代替

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AS374NP1 TI

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 		IC,FLIP-FLOP,OCTAL,D TYPE,AS-TTL,DIP,20PIN,PLASTIC
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 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AS374NSRE4 TI

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 		OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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