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SN74ALVTH16827

更新时间： 2024-11-03 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 输出元件驱动
页数 文件大小 规格书
9页 165K
描述
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74ALVTH16827 数据手册

 浏览型号SN74ALVTH16827的Datasheet PDF文件第2页浏览型号SN74ALVTH16827的Datasheet PDF文件第3页浏览型号SN74ALVTH16827的Datasheet PDF文件第4页浏览型号SN74ALVTH16827的Datasheet PDF文件第5页浏览型号SN74ALVTH16827的Datasheet PDF文件第6页浏览型号SN74ALVTH16827的Datasheet PDF文件第7页 
SN54ALVTH16827, SN74ALVTH16827  
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCES076E – JULY 1996 – REVISED DECEMBER 1998  
SN54ALVTH16827 . . . WD PACKAGE  
SN74ALVTH16827 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low Static  
Power Dissipation  
1OE1  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1OE2  
1A1  
1A2  
GND  
1A3  
1A4  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
3.6-V V  
)
CC  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
V
V
High Drive (–24/24 mA at 2.5-V and  
–32/64 mA at 3.3-V V  
CC  
CC  
1Y5  
1Y6  
1A5  
1A6  
)
CC  
Power Off Disables Outputs, Permitting  
Live Insertion  
1Y7 10  
47 1A7  
GND  
1Y8  
GND  
1A8  
11  
12  
46  
45  
High-Impedance State During Power Up  
and Power Down Prevents Driver Conflict  
1Y9 13  
1Y10 14  
2Y1 15  
2Y2 16  
2Y3 17  
GND 18  
2Y4 19  
2Y5 20  
2Y6 21  
44 1A9  
43 1A10  
42 2A1  
41 2A2  
40 2A3  
39 GND  
38 2A4  
37 2A5  
36 2A6  
Uses Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
Auto3-State Eliminates Bus Current  
Loading When Output Exceeds V  
+ 0.5 V  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model; and Exceeds 1000 V  
Using Charged-Device Model, Robotic  
Method  
V
22  
35  
V
CC  
CC  
2Y7 23  
34 2A7  
33 2A8  
32 GND  
31 2A9  
30 2A10  
29 2OE2  
2Y8 24  
GND 25  
2Y9 26  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
2Y10 27  
2OE1 28  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
description  
The ’ALVTH16827 devices are 20-bit buffers/line drivers designed for 2.5-V or 3.3-V V  
the capability to provide a TTL interface to a 5-V system environment.  
operation, but with  
CC  
The devices are composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer  
section, the two output-enable (1OE1 and 1OE2, or 2OE1 and 2OE2) inputs must be low for the corresponding  
Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the  
high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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