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SN74ALVTH16374DGG

更新时间： 2024-11-18 23:06:15
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德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
16页 419K
描述
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74ALVTH16374DGG 数据手册

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SN54ALVTH16374, SN74ALVTH16374  
2.5-V/3.3-V 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCES068F – JUNE 1996 – REVISED JANUARY 1999  
SN54ALVTH16374 . . . WD PACKAGE  
SN74ALVTH16374 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low Static  
Power Dissipation  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1
2
3
4
5
6
7
8
9
48  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
47 1D1  
46 1D2  
45 GND  
44 1D3  
3.6-V V  
)
CC  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
1D4  
CC  
A
43  
42  
V
V
High Drive (–24/24 mA at 2.5-V and  
–32/64 mA at 3.3-V V  
CC  
CC  
)
1Q5  
1Q6  
41 1D5  
40 1D6  
39 GND  
38 1D7  
37 1D8  
36 2D1  
35 2D2  
34 GND  
33 2D3  
32 2D4  
CC  
Power Off Disables Outputs, Permitting  
Live Insertion  
GND 10  
1Q7 11  
1Q8 12  
2Q1 13  
2Q2 14  
GND 15  
2Q3 16  
2Q4 17  
High-Impedance State During Power Up  
and Power Down Prevents Driver Conflict  
Uses Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
Auto3-State Eliminates Bus Current  
Loading When Output Exceeds V  
+ 0.5 V  
CC  
V
18  
31  
V
CC  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2Q5 19  
2Q6 20  
GND 21  
2Q7 22  
2Q8 23  
2OE 24  
30 2D5  
29 2D6  
28 GND  
27 2D7  
26 2D8  
25 2CLK  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model; and Exceeds 1000 V  
Using Charged-Device Model, Robotic  
Method  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
description  
The ’ALVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V  
or 3.3-V V operation, but with the capability to provide a TTL interface to a 5-V system environment. These  
CC  
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and  
working registers.  
These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock  
(CLK), the flip-flops store the logic levels set up at the data (D) inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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