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SN74ALVTH16240DGGR PDF预览

SN74ALVTH16240DGGR

更新时间： 2024-11-06 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 输出元件驱动
页数 文件大小 规格书
10页 180K
描述
ALVT SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, TSSOP-48

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SN74ALVTH16240DGGR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP48,.3,20
针数：48Reach Compliance Code：not_compliant
风险等级：5.65其他特性：USER SELECTABLE 3V TO 3.6V SUPPLY VOLTAGE
控制类型：ENABLE LOW系列：ALVT
JESD-30 代码：R-PDSO-G48长度：12.5 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
位数：4功能数量：4
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2.5/3.3 V
传播延迟（tpd）：3.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：2.3 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

SN74ALVTH16240DGGR 数据手册

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SN54ALVTH16240, SN74ALVTH16240  
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCES138A – JULY 1998 – REVISED JANUARY 1999  
SN54ALVTH16240 . . . WD PACKAGE  
SN74ALVTH16240 . . . DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Widebus Design for  
2.5-V and 3.3-V Operation and Low Static  
Power Dissipation  
1OE  
1Y1  
1Y2  
GND  
1Y3  
1Y4  
1
2
3
4
5
6
7
8
9
48 2OE  
47 1A1  
46 1A2  
45 GND  
44 1A3  
43 1A4  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 2.3-V to  
3.6-V V  
)
CC  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
High Drive (–24/24 mA at 2.5-V and  
–32/64 mA at 3.3-V V  
V
42  
V
CC  
CC  
)
2Y1  
2Y2  
41 2A1  
40 2A2  
39 GND  
38 2A3  
37 2A4  
36 3A1  
35 3A2  
34 GND  
33 3A3  
32 3A4  
CC  
Power Off Disables Outputs, Permitting  
Live Insertion  
GND 10  
2Y3 11  
2Y4 12  
3Y1 13  
3Y2 14  
GND 15  
3Y3 16  
3Y4 17  
High-Impedance State During Power Up  
and Power Down Prevents Driver Conflict  
Use Bus Hold on Data Inputs in Place of  
External Pullup/Pulldown Resistors to  
Prevent the Bus From Floating  
Auto3-State Eliminates Bus Current  
Loading When Output Exceeds V  
+ 0.5 V  
CC  
V
18  
31  
V
CC  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
4Y1 19  
4Y2 20  
GND 21  
4Y3 22  
4Y4 23  
4OE 24  
30 4A1  
29 4A2  
28 GND  
27 4A3  
26 4A4  
25 3OE  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model; and Exceeds 1000 V  
Using Charged-Device Model, Robotic  
Method  
Flow-Through Architecture Facilitates  
Printed Circuit Board Layout  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), Thin Very  
Small-Outline (DGV) Packages, and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
description  
The ’ALVTH16240 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V V  
the capability to provide a TTL interface to a 5-V system environment.  
operation, but with  
CC  
These devices are designed specifically to improve both the performance and density of 3-state memory  
address drivers, clock drivers, and bus-oriented receivers and transmitters.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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